Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: An autonomous Hardwired Tracking Loop (HWTL) ASIC comprising a HWTL coprocessor provided for implementing most of the receiver processing function for data acquisition and tracking functions of a radio receiver system in dedicated hardware. With the expanded functionality provided by an HWTL coprocessor in the autonomous HWTL ASIC, the interruption of CPU performing the navigation processing is significantly reduced to thereby maximize throughput and minimize power burden on the microprocessor. In the preferred embodiment, the HWTL ASIC also comprises the CPU and a correlator, wherein the correlator provides the high rate greater than approximately 1 KHz signal processing operations, the HWTL coprocessor providing the data acquisition and tracking (medium frequency signal processing) operations, and the CPU thereby freed to provide more bandwidth for lower frequency processing, i.e.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: An autonomous Hardwired Tracking Loop (HWTL) ASIC comprising a HWTL coprocessor provided for implementing most of the receiver processing function for data acquisition and tracking functions of a radio receiver system in dedicated hardware. With the expanded functionality provided by an HWTL coprocessor in the autonomous HWTL ASIC, the interruption of CPU performing the navigation processing is significantly reduced to thereby maximize throughput and minimize power burden on the microprocessor. In the preferred embodiment, the HWTL ASIC also comprises the CPU and a correlator, wherein the correlator provides the high rate greater than approximately 1 KHz signal processing operations, the HWTL coprocessor providing the data acquisition and tracking (medium frequency signal processing) operations, and the CPU thereby freed to provide more bandwidth for lower frequency processing, i.e.

Abstract: An autonomous Hardwired Tracking Loop (HWTL) ASIC comprising a HWTL coprocessor provided for implementing most of the receiver processing function for data acquisition and tracking functions of a radio receiver system in dedicated hardware. With the expanded functionality provided by an HWTL coprocessor in the autonomous HWTL ASIC, the interruption of CPU performing the navigation processing is significantly reduced to thereby maximize throughput and minimize power burden on the microprocessor. In the preferred embodiment, the HWTL ASIC also comprises the CPU and a correlator, wherein the correlator provides the high rate greater than approximately 1 KHz signal processing operations, the HWTL coprocessor providing the data acquisition and tracking (medium frequency signal processing) operations, and the CPU thereby freed to provide more bandwidth for lower frequency processing, i.e.