Abstract: The cell encapsulation system (CES) device is a device used for dermal, subdermal, muscle, tissue, or organ implantation into an individual (host) that is capable of being loaded with and carrying and containing exogenously introduced cells (encapsulated cells) that can produce relevant biochemicals (factors) and/or therapeutic molecules that can be transported to the host tissue while simultaneously not eliciting a significant host immune response (to the implanted device or to the encapsulated cells). The CES device provides a means of local and/or systemic, prolonged delivery of single or multiple factors and/or therapeutic molecules to alleviate, treat, or cure a variety of acute and chronic pathologies and ailments.

Abstract: The cell encapsulation system (CES) device is a device used for dermal, subdermal, muscle, tissue, or organ implantation into an individual (host) that is capable of being loaded with and carrying and containing exogenously introduced cells (encapsulated cells) that can produce relevant biochemicals (factors) and/or therapeutic molecules that can be transported to the host tissue while simultaneously not eliciting a significant host immune response (to the implanted device or to the encapsulated cells). The CES device provides a means of local and/or systemic, prolonged delivery of single or multiple factors and/or therapeutic molecules to alleviate, treat, or cure a variety of acute and chronic pathologies and ailments.

Abstract: Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: A riser for mounting to a rider-support surface of a recreational board and having a binding connected thereto comprises a first plate and a second plate selectively connectable to the first plate along a length of the first plate so as to define a connection location. A plurality of separate and interchangeable dampening members is connectable to each of the first plate and second plate. The plurality of dampening members is spaced along a portion of each first and second plate which is opposite the connection location of the first and second plates. The plurality of dampening members includes a first dampening member and a second dampening member, each having a differing hardness.

Abstract: A riser for mounting to a rider-support surface of a recreational board and having a binder connected thereto comprises a first plate and a second plate selectively connectable to the first plate along a length of the first plate so as to define a connection location. A plurality of separate and interchangeable dampening members is connectable to each of the first plate and second plate. The plurality of dampening members is spaced along a portion of each first and second plate which is opposite the connection location of the first and second plates. The plurality of dampening members includes a first dampening member and a second dampening member, each having a differing hardness.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: A weatherstrip assembly includes a metal surface, a thin tie layer of polymeric material covering at least select portions of the metal surface, and an elastomeric material received over the thin tie layer of polymeric material and exhibiting improved bonding with the metal through the thin layer of polymeric material. Preferably, the thin tie layer is a polypropylene-based olefinic copolymer and an ethylene acrylic acid copolymer.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: Methods for forming a composite for use as a vehicle weather strip and the products formed thereby are disclosed in which a main body member is formed from an elastomer polymer and an abrasion resistant decorative layer including a blend of a crosslinkable thermoplastic polyolefin and a thermoplastic vulcanizate is applied thereon. The crosslinkable thermoplastic polyolefin preferably includes a crosslinkable olefin homopolymer. The olefin homopolymer preferably contains grafted silane functional groups to allow the material to be crosslinked in the presence of moisture. The abrasion resistant decorative layer may be extruded or otherwise applied onto the main body either prior to or after the main body member is cured and either prior to or after the crosslinkable polyolefin of the abrasion resistant decorative layer is crosslinked. The material of the abrasion resistant decorative layer may be extruded into sheet form and laminated onto the main body member.

Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.