Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: A cross-linked, extruded article comprising an elastomeric base material, the surface of which is applied with a thermoset slip coat material, the article exhibiting enhanced slip and a coefficient of friction of no greater than 0.25 and process of making is provided. An extrudable, cross-linkable slip coat comprising a cross-linked thermoset polymer capable of bonding with an elastomeric base material in the absence of adhesive or binder upon contact and process of making is also provided.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: Methods for forming a composite for use as a vehicle weather strip and the products formed thereby are disclosed in which a main body member is formed from an elastomer polymer and an abrasion resistant decorative layer including a blend of a crosslinkable thermoplastic polyolefin and a thermoplastic vulcanizate is applied thereon. The crosslinkable thermoplastic polyolefin preferably includes a crosslinkable olefin homopolymer. The olefin homopolymer preferably contains grafted silane functional groups to allow the material to be crosslinked in the presence of moisture. The abrasion resistant decorative layer may be extruded or otherwise applied onto the main body either prior to or after the main body member is cured and either prior to or after the crosslinkable polyolefin of the abrasion resistant decorative layer is crosslinked. The material of the abrasion resistant decorative layer may be extruded into sheet form and laminated onto the main body member.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: A system and method for controlling and monitoring a wireless communication device. Communication between a communication manager and a wireless communication device is via Ethernet data, and communication between an Ethernet interface controller and a wireless communication module, both in the wireless communication device is via USB data.

Abstract: A system and method for controlling and monitoring a wireless communication device. Communication between a communication manager and a wireless communication device is via Ethernet data, and communication between an Ethernet interface controller and a wireless communication module, both in the wireless communication device is via USB data.

Abstract: A bone plate for fixation of a fractured bone includes a first portion having a first longitudinal axis and a second portion having a second longitudinal axis. The second portion is angled with respect to the first portion. The first portion has at least one hole for receiving a bone anchor having a shaft. The hole has a first hole portion defining a first central axis substantially perpendicular to a lower surface of the first portion and configured to receive the bone anchor. The hole includes a second hole portion overlapping and in communication with the first hole portion from upper to lower surface defining a second central axis substantially angled with respect to the first central axis, and configured to receive the bone anchor such that the shaft is substantially angled with respect to the second portion of the bone plate so as to form a truss.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

Abstract: Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

Abstract: A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

Abstract: Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

Abstract: A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

Abstract: A wireless data terminal apparatus, comprising: a wireless data terminal unit configured to provide data communication over a wireless telecommunication network, the wireless data terminal unit including at least a data processor, an RF section, and a built-in diagnostic unit, wherein the built-in diagnostic unit is configured to process and provide management information of the wireless data terminal unit to enable a browser-based user interface to manage the wireless data terminal unit; and a local area network (LAN) access module coupled to the browser-based user interface and the wireless data terminal unit, the LAN access module including a browser protocol handler to manage user interface functions of the browser-based user interface.