Patents by Inventor Henry Litzmann Edwards

Henry Litzmann Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916067
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 11876134
    Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 16, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Publication number: 20230317846
    Abstract: A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Clint Alan Naquin, Henry Litzmann Edwards, Alexei Sadovnikov
  • Patent number: 11721779
    Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 8, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Rahmi Hezar, Henry Litzmann Edwards
  • Publication number: 20230170414
    Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.
    Type: Application
    Filed: January 13, 2023
    Publication date: June 1, 2023
    Inventor: Henry Litzmann Edwards
  • Publication number: 20230170384
    Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Henry Litzmann Edwards, Joseph Maurice Khayat, Archana Venugopal
  • Publication number: 20230155023
    Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.
    Type: Application
    Filed: November 30, 2021
    Publication date: May 18, 2023
    Inventors: Henry Litzmann Edwards, Andres Arturo Blanco, Orlando Lazaro
  • Publication number: 20230157175
    Abstract: Integrated circuit apparatus, and their manufacturing methods, including an integrated power transistor and thermocouple. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermocouple includes a p-thermopile and an n-thermopile that are each electrically isolated from the power transistor and the semiconductor substrate while being sensitive to temperature differences within the IC resulting from operation of the power transistor. The p-thermopile includes a p-type thermoelectric body formed in a p-type one or more of the plurality of layers. The n-thermopile includes n-type thermoelectric body formed in an n-type one or more of the plurality of layers.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 18, 2023
    Inventors: Henry Litzmann Edwards, Andres Arturo Blanco, Orlando Lazaro
  • Publication number: 20230135889
    Abstract: A method of forming an integrated circuit forms a first oxygen diffusion barrier layer in a fixed position relative to a semiconductor substrate and forms an aperture through the first oxygen diffusion barrier layer to expose a portion of the semiconductor substrate. The method also forms a first LOCOS region in an area of the aperture and a second oxygen diffusion barrier layer along the first LOCOS region and along at least a sidewall portion of the first oxygen diffusion barrier layer in the area of the aperture. The method also deposits a polysilicon layer, at a temperature of 570° C. or less, over the second oxygen diffusion barrier layer, etches the polysilicon layer and the second oxygen diffusion barrier layer to form a spacer in the area of the aperture, and forms a second LOCOS region in the area of the aperture and aligned to the spacer.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Abbas Ali, Christopher Scott Whitesell, John Christopher Shriner, Henry Litzmann Edwards
  • Publication number: 20230115019
    Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 13, 2023
    Inventors: Christopher Boguslaw KOCON, Henry Litzmann EDWARDS
  • Publication number: 20230101691
    Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventor: Henry Litzmann EDWARDS
  • Patent number: 11594630
    Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: February 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Publication number: 20230049751
    Abstract: A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Rahmi HEZAR, Henry Litzmann EDWARDS, Miaad ALIROTEH, Srinath Mathur RAMASWAMY, Baher HAROUN, Gerd SCHUPPENER
  • Patent number: 11574903
    Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 7, 2023
    Assignee: Texas Instmments Incorporated
    Inventors: Henry Litzmann Edwards, Akram A. Salman, Md Iqbal Mahmud
  • Patent number: 11563130
    Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: January 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Becker, Henry Litzmann Edwards
  • Patent number: 11557673
    Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 17, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, Henry Litzmann Edwards
  • Patent number: 11552183
    Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 10, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Andrew D. Strachan
  • Publication number: 20230006060
    Abstract: An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.
    Type: Application
    Filed: February 28, 2022
    Publication date: January 5, 2023
    Inventors: Henry Litzmann Edwards, Narayana Sateesh Pillai, Gangqiang Zhang, Angelo William Pereira
  • Patent number: 11532710
    Abstract: A system and method for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with Shallow Trench Isolation (STI) in the backgate region of FET with trench contacts is provided. The backgate diffusion region of the FET is split in the middle of the source-backgate side of the LDMOS with a strip of STI. A contact can be drawn across STI strip. The contact etch can be etched through the STI fill. The contact barrier material and trench fill processes can create a metal-semiconductor contact in the outline of the STI.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: December 20, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Publication number: 20220392886
    Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 8, 2022
    Inventors: Henry Litzmann EDWARDS, Akram A. SALMAN, Binghua Hu