Patents by Inventor Henry Litzmann Edwards

Henry Litzmann Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11387333
    Abstract: An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 12, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Publication number: 20220208973
    Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.
    Type: Application
    Filed: January 24, 2021
    Publication date: June 30, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Alexei Sadovnikov, Henry Litzmann Edwards, Jarvis Benjamin Jacobs
  • Publication number: 20220209007
    Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Christopher Boguslaw KOCON, Henry Litzmann EDWARDS
  • Patent number: 11374124
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 28, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: James Robert Todd, Xiaoju Wu, Henry Litzmann Edwards, Binghua Hu
  • Publication number: 20220199611
    Abstract: In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Zaichen CHEN, Akram Ali SALMAN, Henry Litzmann EDWARDS
  • Publication number: 20220189949
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Publication number: 20220149186
    Abstract: A semiconductor device including a substrate having a semiconductor layer containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A drain-tied field plate on the field relief dielectric, the drain-tied field plate extending from the drain region toward the gate with an electrical connection between the drain-tied field plate and the drain region.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Gang Xue
  • Patent number: 11296075
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 5, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Publication number: 20220102609
    Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.
    Type: Application
    Filed: December 14, 2021
    Publication date: March 31, 2022
    Inventors: Barry Jon Male, Henry Litzmann Edwards
  • Publication number: 20220068649
    Abstract: A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Inventors: Mona M. Eissa, Jason R. Heine, Pushpa Mahalingam, Henry Litzmann Edwards, James Robert Todd, Alexei Sadovnikov
  • Patent number: 11227986
    Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal. A heater coupled between the input terminal and the return terminal. A thermopile is spaced apart from the heater by a galvanic isolation region. A switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 18, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Henry Litzmann Edwards
  • Publication number: 20210343884
    Abstract: An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 4, 2021
    Inventors: Debarshi Basu, Henry Litzmann Edwards, Ricky A. Jackson, Marco A. Gardner
  • Patent number: 11164969
    Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • Publication number: 20210325443
    Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Inventors: Robert Allan NEIDORFF, Henry Litzmann EDWARDS
  • Patent number: 11152505
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alexei Sadovnikov, Andrew Derek Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu, James Robert Todd
  • Patent number: 11133350
    Abstract: Thermoelectric generator elements and associated circuit elements are simultaneously formed using a common semiconductor device fabrication process to provide an integrated circuit including a dynamically reconfigurable thermoelectric generator array on a common chip or die substrate. A switch logic circuit formed together with the thermoelectric generator elements is configured to control series and parallel connections of the thermoelectric generator elements is the array in response to changes in circuit demand or changes in the available ambient energy source. In an example implementation, the number of generators connected in series may be varied dynamically to provide a stable voltage source, and the number of generators connected in parallel may be varied dynamically to provide a stable current source.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: September 28, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • Patent number: 11094837
    Abstract: An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debarshi Basu, Henry Litzmann Edwards, Ricky A. Jackson, Marco A. Gardner
  • Patent number: 11094817
    Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Patent number: 11085961
    Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 10, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Allan Neidorff, Henry Litzmann Edwards
  • Patent number: 10903356
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Binghua Hu, James Robert Todd