Patents by Inventor Henry Litzmann Edwards
Henry Litzmann Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240230748Abstract: A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.Type: ApplicationFiled: February 15, 2024Publication date: July 11, 2024Inventors: Robert Allan NEIDORFF, Henry Litzmann EDWARDS
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Patent number: 12015057Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.Type: GrantFiled: January 24, 2021Date of Patent: June 18, 2024Assignee: Texas Instruments IncorporatedInventors: Mahalingam Nandakumar, Alexei Sadovnikov, Henry Litzmann Edwards, Jarvis Benjamin Jacobs
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Patent number: 11984504Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.Type: GrantFiled: November 30, 2021Date of Patent: May 14, 2024Assignee: Texas Instruments IncorporatedInventors: Henry Litzmann Edwards, Andres Arturo Blanco, Orlando Lazaro
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Patent number: 11984475Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.Type: GrantFiled: November 29, 2021Date of Patent: May 14, 2024Assignee: Texas Instruments IncorporatedInventors: Henry Litzmann Edwards, Joseph Maurice Khayat, Archana Venugopal
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Patent number: 11984362Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.Type: GrantFiled: August 25, 2021Date of Patent: May 14, 2024Assignee: Texas Instruments IncorporatedInventors: Abbas Ali, Christopher Scott Whitesell, John Christopher Shriner, Henry Litzmann Edwards
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Publication number: 20240105840Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.Type: ApplicationFiled: December 4, 2023Publication date: March 28, 2024Inventor: Henry Litzmann EDWARDS
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Patent number: 11940479Abstract: A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.Type: GrantFiled: June 29, 2021Date of Patent: March 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert Allan Neidorff, Henry Litzmann Edwards
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Patent number: 11925119Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.Type: GrantFiled: December 14, 2021Date of Patent: March 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Henry Litzmann Edwards
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Patent number: 11916067Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: GrantFiled: March 2, 2022Date of Patent: February 27, 2024Assignee: Texas Instruments IncorporatedInventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
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Patent number: 11876134Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.Type: GrantFiled: September 29, 2021Date of Patent: January 16, 2024Assignee: Texas Instruments IncorporatedInventor: Henry Litzmann Edwards
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Publication number: 20230317846Abstract: A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Clint Alan Naquin, Henry Litzmann Edwards, Alexei Sadovnikov
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Patent number: 11721779Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.Type: GrantFiled: April 30, 2021Date of Patent: August 8, 2023Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Henry Litzmann Edwards
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Publication number: 20230170384Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Inventors: Henry Litzmann Edwards, Joseph Maurice Khayat, Archana Venugopal
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Publication number: 20230170414Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.Type: ApplicationFiled: January 13, 2023Publication date: June 1, 2023Inventor: Henry Litzmann Edwards
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Publication number: 20230155023Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.Type: ApplicationFiled: November 30, 2021Publication date: May 18, 2023Inventors: Henry Litzmann Edwards, Andres Arturo Blanco, Orlando Lazaro
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Publication number: 20230157175Abstract: Integrated circuit apparatus, and their manufacturing methods, including an integrated power transistor and thermocouple. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermocouple includes a p-thermopile and an n-thermopile that are each electrically isolated from the power transistor and the semiconductor substrate while being sensitive to temperature differences within the IC resulting from operation of the power transistor. The p-thermopile includes a p-type thermoelectric body formed in a p-type one or more of the plurality of layers. The n-thermopile includes n-type thermoelectric body formed in an n-type one or more of the plurality of layers.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Inventors: Henry Litzmann Edwards, Andres Arturo Blanco, Orlando Lazaro
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Publication number: 20230135889Abstract: A method of forming an integrated circuit forms a first oxygen diffusion barrier layer in a fixed position relative to a semiconductor substrate and forms an aperture through the first oxygen diffusion barrier layer to expose a portion of the semiconductor substrate. The method also forms a first LOCOS region in an area of the aperture and a second oxygen diffusion barrier layer along the first LOCOS region and along at least a sidewall portion of the first oxygen diffusion barrier layer in the area of the aperture. The method also deposits a polysilicon layer, at a temperature of 570° C. or less, over the second oxygen diffusion barrier layer, etches the polysilicon layer and the second oxygen diffusion barrier layer to form a spacer in the area of the aperture, and forms a second LOCOS region in the area of the aperture and aligned to the spacer.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Abbas Ali, Christopher Scott Whitesell, John Christopher Shriner, Henry Litzmann Edwards
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Publication number: 20230115019Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.Type: ApplicationFiled: December 15, 2022Publication date: April 13, 2023Inventors: Christopher Boguslaw KOCON, Henry Litzmann EDWARDS
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Publication number: 20230101691Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventor: Henry Litzmann EDWARDS
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Patent number: 11594630Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.Type: GrantFiled: May 25, 2021Date of Patent: February 28, 2023Assignee: Texas Instruments IncorporatedInventor: Henry Litzmann Edwards