Patents by Inventor Henry Litzmann Edwards

Henry Litzmann Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903356
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Binghua Hu, James Robert Todd
  • Publication number: 20210005599
    Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Patent number: 10879387
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Patent number: 10861948
    Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Binghua Hu, James Robert Todd
  • Publication number: 20200303491
    Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Inventor: HENRY LITZMANN EDWARDS
  • Publication number: 20200303518
    Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Inventors: Henry Litzmann EDWARDS, Andrew D. STRACHAN
  • Patent number: 10784251
    Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Publication number: 20200266306
    Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: James Becker, Henry Litzmann Edwards
  • Patent number: 10714594
    Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Andrew D. Strachan
  • Patent number: 10707296
    Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • Publication number: 20200200815
    Abstract: An example method comprises providing a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method comprises using the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also includes using the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further comprises using the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Robert Allan NEIDORFF, Henry Litzmann EDWARDS
  • Publication number: 20200176659
    Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal. A heater coupled between the input terminal and the return terminal. A thermopile is spaced apart from the heater by a galvanic isolation region. A switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Barry Jon Male, Henry Litzmann Edwards
  • Publication number: 20200161471
    Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Patent number: 10644173
    Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Becker, Henry Litzmann Edwards
  • Patent number: 10636933
    Abstract: A photodetector cell includes a substrate having a semiconductor surface layer, and a trench in the semiconductor surface layer. The trench has tilted sidewalls including a first tilted sidewall and a second tilted sidewall. A pn junction, a PIN structure, or a phototransistor includes an active p-region and an active n-region that forms a junction including a first junction along the first tilted sidewall to provide a first photodetector element and a second junction spaced apart from the first junction along the second tilted sidewall to provide a second photodetector element. At least a p-type anode contact and at least an n-type cathode contact contacts the active p-region and active n-region of the first photodetector element and second photodetector element. The tilted sidewalls provide an outer exposed or optically transparent surface for passing incident light to the first and second photodetector elements for detection of incident light.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Henry Litzmann Edwards
  • Publication number: 20200119149
    Abstract: An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 16, 2020
    Inventor: HENRY LITZMANN EDWARDS
  • Publication number: 20200119133
    Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventor: HENRY LITZMANN EDWARDS
  • Publication number: 20200083336
    Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Henry Litzmann Edwards, Binghua Hu, James Robert Todd
  • Publication number: 20200075583
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 10580890
    Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards