Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal. A heater coupled between the input terminal and the return terminal. A thermopile is spaced apart from the heater by a galvanic isolation region. A switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.

Abstract: An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone.

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

Abstract: Thermoelectric generator elements and associated circuit elements are simultaneously formed using a common semiconductor device fabrication process to provide an integrated circuit including a dynamically reconfigurable thermoelectric generator array on a common chip or die substrate. A switch logic circuit formed together with the thermoelectric generator elements is configured to control series and parallel connections of the thermoelectric generator elements is the array in response to changes in circuit demand or changes in the available ambient energy source. In an example implementation, the number of generators connected in series may be varied dynamically to provide a stable voltage source, and the number of generators connected in parallel may be varied dynamically to provide a stable current source.

Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.

Abstract: An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone.

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.

Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.

Abstract: An example method comprises providing a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method comprises using the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also includes using the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further comprises using the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.