Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light.

Abstract: A semiconductor device contains a photodiode which has a plurality of p-n junctions disposed in a stack. Two contact structures on the semiconductor device are connected across at least one of the junctions to allow electrical connection to an external detection circuit, so that signal current from incident light on the photodiode which generates electron-hole pairs across the connected junction may be sensed by the external detection circuit. At least one of the junctions is electrically shorted at the semiconductor device, so that signal current from the shorted junction may not be sensed by the external detection circuit.

Abstract: A semiconductor device contains a photodiode which includes a buried collection region formed by a bandgap well to vertically confine photo-generated minority carriers. the bandgap well has the same conductivity as the semiconductor material immediately above and below the bandgap well. A net average doping density in the bandgap well is at least a factor of ten less than net average doping densities immediately above and below the bandgap well. A node of the photodiode, either the anode or the cathode, is connected to the buried collection region to collect the minority carriers, the polarity of the node matches the polarity of the minority carriers. The photodiode node connected to the buried collection region occupies less lateral area than the lateral area of the buried collection region.

Abstract: A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract: A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.

Abstract: A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor.

Abstract: A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.

Abstract: Thermoelectric generator elements and associated circuit elements are simultaneously formed using a common semiconductor device fabrication process to provide an integrated circuit including a dynamically reconfigurable thermoelectric generator array on a common chip or die substrate. A switch logic circuit formed together with the thermoelectric generator elements is configured to control series and parallel connections of the thermoelectric generator elements is the array in response to changes in circuit demand or changes in the available ambient energy source. In an example implementation, the number of generators connected in series may be varied dynamically to provide a stable voltage source, and the number of generators connected in parallel may be varied dynamically to provide a stable current source.

Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.

Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.

Abstract: A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.

Abstract: A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor.

Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.

Abstract: One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.

Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.

Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.