Abstract: A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.

Abstract: A process for providing one or more protected copper elements on a surface of a workpiece is set forth. In accordance with the process, a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for subsequent electroplating processes, a separate seed layer is applied over the surface of the barrier layer. One or more copper elements are then electroplated on selected portions of the seed layer or, if suitable, the barrier layer. If used, the seed layer is then substantially removed. At least a portion of a surface of the barrier layer is rendered unplatable while leaving the copper elements suitable for electroplating. A protective layer is then electroplated onto surfaces of the one or more copper elements.

Abstract: A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.

Abstract: A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.

Abstract: A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at least one thin-film layer and the etching of the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.

Abstract: A manufacturing tool configuration for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed. The tool configuration comprises a film deposition tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set.

Abstract: A manufacturing tool configuration for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed. The tool configuration comprises a film deposition tool set, a hard mask formation tool set, a hard mask etching tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set. The film deposition tool set is used to deposit a conductive barrier layer exterior to the planar dielectric surface of the workpiece and a conductive seed layer exterior to the barrier layer. The hard mask formation tool set is used to form a hard mask dielectric layer exterior to the seed layer in accordance with one of the disclosed processes, and to form a still further hard mask dielectric layer exterior to the hard mask dielectric layer.

Abstract: A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects.

Abstract: In fabricating a source/drain electrode of an integrated circuit transistor and a contact window for it: (1) establishing a structure with a window over the source/drain region next to a gate electrode and isolation structure; (2) establishing a dielectric layer covering the isolation structure, the window, and gate electrode; (3) implanting a moderate concentration of impurities into the source/drain region through said dielectric layer so that the moderate concentration region extends partially under the gate electrode; (4) removing the horizontal portions of the dielectric layer with an anisotropic etch thereby leaving the dielectric on vertical side walls; (5) establishing a region of titanium silicide over the moderately dosed source/drain region and establishing a titanium nitride layer over the isolation structure, windows, and gate electrode; (6) establishing a layer of silicon nitride over the titanium nitride layer; (7) implanting the substrate with a relatively heavier dose of ions through the sili

Abstract: A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects.

Abstract: In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

Abstract: A reaction barrier is formed at an interface region between adjacent layers of a multilayer composite integrated circuit by implanting one or more active ionic species at energies effective to place the ionic species at or near the interface. A further step may include annealing the structure formed above to promote efficacy of the reaction barrier.

Abstract: An improved structure and process for contacting and interconnecting semiconductor devices within a VLSI integrated circuit are described. The structure includes several regions which cooperate to provide (1) contacts of low electrical resistance to semiconductor device terminals, (2) barriers to unwanted metallurgic reactions, (3) strong bonds between major regions of the structure, (4) overall mechanical strength, (5) a primary current path of low electrical resistance, (6) a secondary current path in parallel with the primary current path, and (7) circuit bond pads for use in making electrical connections to the VLSI circuit. Because of the structure's mechanical strength, semiconductor devices may be placed beneath circuit bond pads. The inventive process facilitates accurate control of the composition and thickness of each of the several regions within the material structure.

Abstract: An improved structure and process for contacting and interconnecting semiconductor devices within a VLSI integrated circuit are described. The structure includes several regions which cooperate to provide (1) contacts of low electrical resistance to semiconductor device terminals, (2) barriers to unwanted metallurgic reactions, (3) strong bonds between major regions of the structure, (4) overall mechanical strength, (5) a primary current path of low electrical resistance, (6) a secondary current path in parallel with the primary current path, and (7) circuit bond pads for use in making electrical connections to the VLSI circuit. Because of the structure's mechanical strength, semiconductor devices may be placed beneath circuit bond pads. The inventive process facilitates accurate control of the composition and thickness of each of the several regions within the material structure.

Abstract: A titanium silicide/titanium nitride process is disclosed wherein the thickness of the titanium nitride can be regulated with respect to the titanium silicide. In particular, a control layer is formed in the contact opening during a reactive cycle to form a relatively thin (20 to 50 angstrom) control layer. Titanium is thereafter deposited and in another thermal reaction the control layer retards the development of titanium silicide without retarding the development of titanium nitride so that the thickness of titanium silicide is kept small. A double titanium process can also be used.