Patents by Inventor Henry Wei-Ming Chung
Henry Wei-Ming Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7605414Abstract: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.Type: GrantFiled: January 24, 2005Date of Patent: October 20, 2009Assignee: Macronix International Co., Ltd.Inventor: Henry Wei-Ming Chung
-
Patent number: 7541271Abstract: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity silicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.Type: GrantFiled: May 2, 2007Date of Patent: June 2, 2009Assignee: Macronix International Co., Ltd.Inventor: Henry Wei-Ming Chung
-
Patent number: 7361604Abstract: A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.Type: GrantFiled: June 20, 2003Date of Patent: April 22, 2008Assignee: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Patent number: 7303995Abstract: A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.Type: GrantFiled: June 20, 2003Date of Patent: December 4, 2007Assignee: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Patent number: 7033948Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.Type: GrantFiled: December 19, 2003Date of Patent: April 25, 2006Assignee: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Patent number: 6887627Abstract: A method of fabricating a phase shift mask (PSM) is described. A patterned photoresist layer is formed on an opaque layer over a transparent plate. A thin mask layer is formed on the sidewalls of the patterned photoresist layer. The exposed opaque layer and transparent plate thereunder are then removed while using the patterned photoresist layer and mask layer as a mask. A phase shift opening is formed in the transparent plate, and thereby a phase shift layer is formed at the place where the phase shift opening is located. The patterned photoresist layer and the opaque layer thereunder are then removed to expose the transparent plate. The opaque layer under the mask layer can precisely self-align the phase shift layer to prevent alignment deviation caused by multiple lithography processes. The precision of the phase shift mask can be increased, and mask manufacture cost can be lowered.Type: GrantFiled: April 26, 2002Date of Patent: May 3, 2005Assignee: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Chi-Yuan Hung, Ching-Yu Chang, I-Pien Wu
-
Patent number: 6809018Abstract: A method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor and a second transistor thereon. The top surface of the first transistor's gate is higher than that of the second transistors' gate. The mask layer is patterned to expose the top surface of the second transistor's gate, source and drain. First metal suicides are formed respectively on the top surfaces of the second transistor's gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor's gate. The dielectric layer, higher than the top surface of the second transistor's gate, is removed to expose the top surfaces of the first and the second transistors' gates. A second metal silicide is formed on the top surface of the first transistor's gate.Type: GrantFiled: July 11, 2002Date of Patent: October 26, 2004Assignee: Macronix International Co., Ltd.Inventor: Henry Wei-Ming Chung
-
Publication number: 20040132225Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.Type: ApplicationFiled: December 19, 2003Publication date: July 8, 2004Applicant: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Patent number: 6750150Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.Type: GrantFiled: October 18, 2001Date of Patent: June 15, 2004Assignee: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Patent number: 6709923Abstract: The present invention discloses a method for manufacturing an array structure in integrated circuits (IC). The method for manufacturing an array structure in integrated circuits of the present invention is performed by using two masks. First, a first mask having array pattern of holes is used to perform a first exposing step with a partial dose, and a second mask having code patterns is used to perform a second exposing step with a compensating dose for the first exposing step, so that a photoresist covering the regions of the holes desired to be opened obtains a sufficient exposure dose and the holes desired are formed by developing. Therefore, a preferred resolution and a preferred depth of focus (DOF) for exposure are obtained, thereby reducing optical proximity effect (OPE), and it is quite easily to manufacture the masks used in the present invention.Type: GrantFiled: June 25, 2002Date of Patent: March 23, 2004Assignee: Macronix International Co., Ltd.Inventor: Henry Wei-Ming Chung
-
Publication number: 20040018697Abstract: A method and structure for interconnection fabrication by using dielectric anti-reflection coating to improve the photolithographic process. The device's structure comprises a substrate with a Cu or Cu-based alloy formed therein. After planarizing the device, a thin barrier dielectric layer is formed on the substrate. A dielectric anti-reflection coating (DARC) layer is then formed on the barrier dielectric layer. Next, another inter-layer dielectric is formed on the anti-reflective coating layer and a subsequent photoresist layer is formed on the inter-reflection coating layer and patterned by using the underlying DARC layer to reduce the light reflection. By using the structure and method of the present invention, it is possible to decrease the process steps and increase the precision of the photolithographic process.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Inventor: Henry Wei-Ming Chung
-
Publication number: 20040009652Abstract: A method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor and a second transistor thereon. The top surface of the first transistor's gate is higher than that of the second transistors' gate. The mask layer is patterned to expose the top surface of the second transistor's gate, source and drain. First metal suicides are formed respectively on the top surfaces of the second transistor's gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor's gate. The dielectric layer, higher than the top surface of the second transistor's gate, is removed to expose the top surfaces of the first and the second transistors' gates. A second metal silicide is formed on the top surface of the first transistor's gate.Type: ApplicationFiled: July 11, 2002Publication date: January 15, 2004Inventor: Henry Wei-Ming Chung
-
Publication number: 20030235950Abstract: The present invention discloses a method for manufacturing an array structure in integrated circuits (IC). The method for manufacturing an array structure in integrated circuits of the present invention is performed by using two masks. First, a first mask having array pattern of holes is used to perform a first exposing step with a partial dose, and a second mask having code patterns is used to perform a second exposing step with a compensating dose for the first exposing step, so that a photoresist covering the regions of the holes desired to be opened obtains a sufficient exposure dose and the holes desired are formed by developing. Therefore, a preferred resolution and a preferred depth of focus (DOF) for exposure are obtained, thereby reducing optical proximity effect (OPE), and it is quite easily to manufacture the masks used in the present invention.Type: ApplicationFiled: June 25, 2002Publication date: December 25, 2003Applicant: Macronix International Co., Ltd.Inventor: Henry Wei-Ming Chung
-
Publication number: 20030224602Abstract: A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.Type: ApplicationFiled: June 20, 2003Publication date: December 4, 2003Applicant: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Publication number: 20030224254Abstract: A method for manufacturing a photomask is provided. A transparent substrate is provided and a mask layer is formed thereon. A resist layer is formed on the mask layer and then patterned and defined to define a critical dimension of the photomask. A third layer is deposited over the patterned and defined resist layer to decrease the critical dimension of the photomask. And the third layer and the mask layer are etched afterwards.Type: ApplicationFiled: June 20, 2003Publication date: December 4, 2003Applicant: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Publication number: 20030216051Abstract: A semiconductor manufacturing method that includes providing a substrate, providing a layer of semiconductor material over the substrate, providing a layer of photoresist over the semiconductor material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of semiconductor material.Type: ApplicationFiled: June 20, 2003Publication date: November 20, 2003Applicant: Macronix International Co., Ltd.Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Publication number: 20030203285Abstract: A method of fabricating a phase shift mask (PSM) is described. A patterned photoresist layer is formed on an opaque layer over a transparent plate. A thin mask layer is formed on the sidewalls of the patterned photoresist layer. The exposed opaque layer and transparent plate thereunder are then removed while using the patterned photoresist layer and mask layer as a mask. A phase shift opening is formed in the transparent plate, and thereby a phase shift layer is formed at the place where the phase shift opening is located. The patterned photoresist layer and the opaque layer thereunder are then removed to expose the transparent plate. The opaque layer under the mask layer can precisely self-align the phase shift layer to prevent alignment deviation caused by multiple lithography processes. The precision of the phase shift mask can be increased, and mask manufacture cost can be lowered.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Inventors: Henry Wei-Ming Chung, Chi-Yuan Hung, Ching-Yu Chang, I-Pien Wu
-
Publication number: 20030082916Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.Type: ApplicationFiled: October 18, 2001Publication date: May 1, 2003Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
-
Publication number: 20020151165Abstract: An interconnection scheme employing a dual damascene configuration for coupling multi-layer interconnects is presented. The interconnection structure includes an underlying conductive region, generally comprised of a copper or copper-based alloy having a via hole formed thereupon, with a subsequent trench region formed yet thereupon. The via hole and trench regions are coated both on the horizontal and vertical facet with a barrier material which is thereafter anisotropically etched to remove the horizontal segments of the barrier layer. The horizontal segment attached to the conductive region of the underlying conductor is also removed such that the conductive layer formed within the trench and via hole regions directly contact the underlying conductive region. Such a direct interface forgoes the problems present in material dissimilarities and also provides an improved resistivity match.Type: ApplicationFiled: April 17, 2001Publication date: October 17, 2002Inventor: Henry Wei-Ming Chung
-
Patent number: 5858875Abstract: A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer includes a dielectric layer having a trench formed therein, the trench being filled with a plug material. The foundation layer further includes a barrier layer formed atop the dielectric layer. A metal layer is formed on the surface of the boundary layer, and a protection layer is formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the boundary layer. An etch stop layer is formed which substantially conforms to the shape of the composite protection/metal line, including etch stop spacers conforming to the sidewall portions of the line.Type: GrantFiled: November 13, 1996Date of Patent: January 12, 1999Assignee: National Semiconductor CorporationInventors: Henry Wei-Ming Chung, Kevin Carl Brown