Patents by Inventor Henry Wong

Henry Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10284397
    Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 7, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuchun Lu, Henry Wong, Davide Tonietto
  • Publication number: 20190028236
    Abstract: Methods, systems and computer-readable media for optimizing SerDes system parameters based on a bit error rate detected by a forward error correction unit (FEC). A SerDes receiver receives a data stream over a link and uses a FEC to detect error information in the received data stream. The system tunes and optimizes one or more SerDes system parameters using the detected error information. The system minimizes power consumption by decreasing power supply voltage until a maximum acceptable input error rate threshold is reached. The FEC allows the system to tolerate errors in the input data stream up to the threshold while preventing propagation of these errors in the FEC output data stream.
    Type: Application
    Filed: July 21, 2017
    Publication date: January 24, 2019
    Inventors: DAVIDE TONIETTO, MARC-ANDRE LACROIX, HENRY WONG
  • Publication number: 20180278444
    Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Inventors: Yuchun Lu, Henry Wong, Davide Tonietto
  • Publication number: 20180205692
    Abstract: A group of post data items may be identified at a first location. Presentation of the group of post data items may be provided at a second location. A post data item in the group of post data items at the second location may be identified where the post data item is in reply to another post data item in the group of post data item. A user may be identified for notification of the post data item. A determination of whether the user interacted with the group of post data items at the first location or the second location is made and a notification for the user that includes a reference to the group of post data items at the first location or the second location is provided.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 19, 2018
    Inventors: Yonatan Zunger, Lan Liu, Justin Lewis, Cynthia Johanson, Henry Wong, Nundu Janakiram, Prasenjit Sarkar, Brett Hobbs, John Fisher, Dan Peterson
  • Patent number: 10009035
    Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 26, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Marc-Andre LaCroix, Semyon Lebedev, Henry Wong, Davide Tonietto
  • Patent number: 10003481
    Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 19, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuchun Lu, Henry Wong, Davide Tonietto
  • Patent number: 9935910
    Abstract: In one aspect, a method is provided, including the following method operations: receiving a request to generate a first post data item at a first location; providing for presentation of the first post data item at a second location; receiving a request to generate a second post data item at the second location, the second post data item being in reply to the first post data item; identifying a destination for notification about the second post data item; providing in association with the destination a notification identifying the second post data item, the notification being associated with the first location.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 3, 2018
    Assignee: GOOGLE LLC
    Inventors: Yonatan Zunger, Lan Liu, Justin Lewis, Cynthia Johanson, Henry Wong, Nundu Janakiram, Prasenjit Sarkar, Brett Hobbs, John Fisher, Dan Peterson
  • Publication number: 20170317857
    Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Yuchun Lu, Henry Wong, Davide Tonietto
  • Patent number: 9712349
    Abstract: A system and method for Feed Forward. Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 18, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuchun Lu, Henry Wong, Davide Tonietto
  • Patent number: 9553600
    Abstract: The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 24, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Marc-Andre Lacroix, Henry Wong, Davide Tonietto
  • Patent number: 9515785
    Abstract: Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: December 6, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Davide Tonietto, Henry Wong
  • Patent number: 9473033
    Abstract: A two-terminal device that is configured to respond to a voltage modulation of an input signal received through the two terminals by triggering an action. The two-terminal device is further configured to verify a result of the triggered action by modulating a current driven through the two termi+6nals.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: October 18, 2016
    Assignee: DIALOG SEMICONDUCTOR, INC.
    Inventors: Kai-Wen Chin, John Kesterson, Fuqiang Shi, Henry Wong, Pengju Kong
  • Patent number: 9444615
    Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: September 13, 2016
    Assignee: Semtech Canada Corporation
    Inventors: Andrew Marshall, Henry Wong, Essaid Bensoudane
  • Publication number: 20160239869
    Abstract: Apparatuses, systems, and processes are discussed for an advertisement network including an analytics engine, an Ad server, and a database. The analytics engine can be configured to collect and analyze signal data about tracked statistics and data on advertising effectiveness and search information. The analytics engine can also be configured to work with the Ad server. The database can be configured to store multiple instances of one or more product video advertisements, each of the multiple instances varying in content and containing an embedded link. The database can have an index of the multiple instances of the one or more product video advertisements. The analytics engine can be configured to work with the Ad server to select and deliver a first instance of a product video advertisement optimized for a search engine-results page based on the signal data.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 18, 2016
    Inventors: Henry Wong, Jay DeDapper, Kelly Dyer
  • Patent number: 9413249
    Abstract: A switching power converter provides regulated voltage to a load. The switching power converter comprises a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the switching power converter. The switching power converter further comprises a power switch coupled to the primary winding and a rectifier coupled to the secondary winding. Current is generated in the primary winding responsive to the power switch being turned on and not generated responsive to the power switch being turned off. A detection circuit measures a voltage across the rectifier. If the detection circuit detects a decrease in the voltage across the rectifier outside of a blanking period, the detection circuit generates a current pulse in the secondary winding of the transformer. A fast power-on-reset device generates a startup signal to activate the detection circuit at an end of the blanking period.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 9, 2016
    Assignee: Dialog Semiconductor Inc.
    Inventors: Pengju Kong, Henry Wong, Wesley Ma, Judy Sha
  • Publication number: 20160173240
    Abstract: Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Davide Tonietto, Henry Wong
  • Publication number: 20160164419
    Abstract: A two-terminal device that is configured to respond to a voltage modulation of an input signal received through the two terminals by triggering an action. The two-terminal device is further configured to verify a result of the triggered action by modulating a current driven through the two termi+6nals.
    Type: Application
    Filed: December 29, 2014
    Publication date: June 9, 2016
    Inventors: Kai-Wen Chin, John Kesterson, John Shi, Henry Wong, Pengju Kong
  • Publication number: 20160142358
    Abstract: In one aspect, a method is provided, including the following method operations: receiving a request to generate a first post data item at a first location; providing for presentation of the first post data item at a second location; receiving a request to generate a second post data item at the second location, the second post data item being in reply to the first post data item; identifying a destination for notification about the second post data item; providing in association with the destination a notification identifying the second post data item, the notification being associated with the first location.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 19, 2016
    Applicant: Google Inc.
    Inventors: Yonatan Zunger, Lan Liu, Justin Lewis, Cynthia Johanson, Henry Wong, Nundu Janakiram, Prasenjit Sarkar, Brett Hobbs, John Fisher, Dan Peterson
  • Publication number: 20160028314
    Abstract: A switching power converter provides regulated voltage to a load. The switching power converter comprises a transformer including a primary winding coupled to an input voltage and a secondary winding coupled to an output of the switching power converter. The switching power converter further comprises a power switch coupled to the primary winding and a rectifier coupled to the secondary winding. Current is generated in the primary winding responsive to the power switch being turned on and not generated responsive to the power switch being turned off. A detection circuit measures a voltage across the rectifier. If the detection circuit detects a decrease in the voltage across the rectifier outside of a blanking period, the detection circuit generates a current pulse in the secondary winding of the transformer. A fast power-on-reset device generates a startup signal to activate the detection circuit at an end of the blanking period.
    Type: Application
    Filed: December 1, 2014
    Publication date: January 28, 2016
    Inventors: Pengju Kong, Henry Wong, Wesley Ma, Judy Sha
  • Publication number: 20150146834
    Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.
    Type: Application
    Filed: July 25, 2011
    Publication date: May 28, 2015
    Applicant: SEMTECH Canada Corporation
    Inventors: Andrew Marshall, Henry Wong, Essaid Bensoudane