Abstract: A semiconductor device having a double spacer and a method of manufacturing the device are provided. The semiconductor device includes a first spacer formed on the sidewall of a gate electrode and a second spacer formed on the slanted sidewall of the first spacer. A first impurity region is formed doped with a first conductivity type impurity at a first concentration and formed at a small junction depth in the substrate to self-align at the edge of the gate electrode. A second impurity region doped with a second conductivity type impurity at a second concentration is formed at a large junction depth in the substrate to self-align at the edge of the first spacer. A third impurity region doped with the first conductivity type impurity at a third concentration is formed at a medium junction depth in the second impurity region to self-align at the edge of the second spacer.

Abstract: A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove being in contact with at least one side face of the impurity-doped region, a conductive layer buried in the trench, and a contact region formed on at least one side face of the impurity-doped region, for connecting the impurity-doped region and the conductive layer. Thus, the area occupied by a unit cell is reduced and integration density can be increased accordingly.

Abstract: A method of forming a side contact in a semiconductor device wherein a first insulating layer, first conductive and second insulating layer are formed over a substrate, and a contact hole through these layers exposes a portion of the substrate and a side edge of the first conductive layer. A refractory metal layer being formed in the contact hole, such that the natural oxide layer is changed into a conductive material by reaction with the refractory metal layer during a subsequent process step.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.

Abstract: A semiconductor device having a silicide layer with substantially even thickness, and a method for making a silicide layer having substantially even thickness in a semiconductor device are disclosed.A prefereably doped polycrystalline silicon layer is formed as a first conductive layer on an insulating underneath layer. After that, an undoped polycrystalline silicon is deposited on the first conductive layer as a buffer layer for preventing silicon diffusion. A second conductive layer is formed thereon. Subsequently, a refractory metal layer is formed on the second conductive layer, and a heating treatment is carried out to form a silicide layer on the first conductive layer from the materials of the buffer layer, second conductive layer and refractory metal layer.

Abstract: A static random access memory (SRAM) device and a manufacturing method thereof are provided. In the SRAM memory device, a first active region of annular shape and a second active region bisecting the annulus are repeatedly formed over the whole cell array. Thus, since the contact hole for connecting the power line to the active region can be formed larger without increasing the cell size, contact resistance can be decreased. Also, the manufacturing method can be simplified since just one gate oxide layer formation process is needed.