Abstract: A method of fabricating a plurality of spaced apart submicron memory cells is disclosed, including the steps of depositing a magnetoresistive system on a substrate formation, depositing and patterning a first layer of material to form sidewalls, and depositing a second, selectively etchable, layer of material on the first layer of material, etching the second layer of material to define spacers on the sidewalls of the first layer of material, etching the magnetoresistive system, using the spacers as a mask, to define a plurality of spaced apart submicron magnetic memory cells, and depositing electrical contacts on the plurality of spaced apart submicron magnetic memory cells.

Abstract: A method of masking surfaces during fabrication of semiconductor devices is disclosed, which includes providing a substrate, and in a preferred embodiment a silicon substrate. The surface is hydrogen terminated (or hydrogenated) and a metal mask is positioned on the surface so as to define a growth area and an unmasked portion on the surface. Ozone is generated at the surface, at least in the unmasked area, by exposing the surface to a light having a wavelength approximately 185 nm (an oxygen absorbing peak), so as to grow an oxide film on the unmasked portion of the surface. The metal mask is removed and the oxide film then serves as a mask for further operations and can be easily removed in situ by heating.

Abstract: Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.

Abstract: A multi-layer magnetic memory cell including two similar layers of magnetic material stacked in parallel, overlying relationship and separated by a layer of non-magnetic material. Each of the two similar layers have a width that is less than a width of magnetic domain walls within the layer of magnetic material so that magnetic vectors in the two similar layers point along the length thereof. The two similar layers define a central plane parallel with the two similar layers symmetrically formed and positioned thereabout. Magnetic vectors in the two similar layers are switched simultaneously and the two similar layers are positioned close enough together to allow mutual cancellation of pole effects during simultaneous switching of the magnetic vectors.

Abstract: A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.

Abstract: A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

Abstract: A magnetic random access memory (MRAM) cell structure (10) with a portion of giant magnetoresistive (GMR) material (11), around which single or multiple word line (12) is wound, is provided. Magnetic field generated by word current (13, 14) superimposed in portion of GMR material (11) so that a total strength of magnetic field increases proportionally. The same word current is passed through the portion of GMR material (11) multiple times, thus producing equivalent word field by many times as large word current in a conventional MRAM cell.

Abstract: A process for manufacturing of a field emission device (100, 200) including the steps of i) providing a substrate (101, 201), ii) forming a conductive row (106, 206), ii) forming a dielectric layer (102, 202), iv) forming a resist layer (116, 216), v) forming a self-assembled monolayer (112, 212) of a self-assembled monolayer-forming molecular species on the resist layer (116, 216) so that the self-assembled monolayer (112, 212) defines an etch pattern for an emitter well (107, 207), vi) etching the resist layer (116, 216), vii) etching the dielectric layer ((102, 202), viii) forming conductive column (103, 203), and ix) forming the electron-emitter structure (105, 208) within the emitter well (107, 207).

Abstract: An apparatus (95) and method for patterning a surface of an article (30), the apparatus (95) including a large-area stamp (50) for forming a self-assembled monolayer (36) (SAM) of a molecular species (38) on the surface (34) of a layer (32) of resist material, which is formed on the surface of the article (30). The large-area stamp (50) includes a layer (52) of an elastomer and has, embedded within it, mechanical structures (68, 80) which stiffen the large-area stamp (50) and deform it to control the stamped patterns. The method includes the steps of: forming a layer (32) of resist material is on the surface of the article (30), utilizing the large-area stamp (50) to form the SAM (36) on the surface (34) of the layer (32) of resist material, etching the layer (32) of resist material, and thereafter etching or plating the surface of the article (30).

Abstract: A tunnel transistor including source and drain and a silicon oxide tunneling layer overlying the source. A polysilicon quantum well layer positioned on the tunneling layer and in contact with the drain. The quantum well layer having a thickness which places the ground state above the Fermi level. A silicon oxide insulating layer positioned on the quantum well layer and a gate electrode positioned on the insulating layer overlying the quantum well layer and the source terminal. The tunneling layer being thin enough to allow tunneling between the source and the quantum well layer, and the insulating layer being thick enough to prevent tunneling therethrough.

Abstract: Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.

Abstract: Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.

Abstract: A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.

Abstract: A high density multistate SRAM cell including N negative differential resistance diodes connected in series and to a load. The diodes and the load defining a memory node having N+1 stable states. A write transistor having a drain connected to the memory node and adapted to receive N+1 different amplitudes of voltage on the source, and a write signal on the gate. An amplifier having an input terminal connected to the memory node, and a read switch having an input terminal connected to the output terminal of the amplifier. A plurality of cells connected into a matrix with N+1 sense amplifiers associated with each column of the matrix so as to provide an output for each of the N+1 different amplitudes.

Abstract: An SRAM including first and second RITDs each formed with a heterostructure including a GaSb active layer sandwiched between AlSb barrier layers, which are sandwiched between InAs layers with each RITD having a contact connected to a first of the InAs layers. A TD including an AlSb layer sandwiched between InAS layers. A second InAs layer for each of the RITDs being integrally formed with a first InAs layer of the TD and a read/write terminal connected to a second InAs layer of the TD.

Abstract: A resonant tunneling FET including a heterostructure FET with a channel layer having a first current contact and a control contact operatively coupled thereto and a resonant tunneling device, including a quantum well layer sandwiched between barrier layers with a resonant tunneling layer affixed to an opposite side of one barrier layer, operably affixed to the heterostructure FET to form a second current contact. The resonant tunneling FET being constructed from a material system which allows the fabrication of additional devices on the same substrate.

Abstract: A band-to-band resonant tunneling transistor including GaSb and InAs resonant tunneling layers separated by a thin barrier layer and a second InAs layer separated from the GaSb layer by another thin barrier layer. A terminal on the InAs resonant tunneling layer and a terminal on the second InAs layer. Leakage current reduction layers are positioned on the second InAs layer with a bias terminal positioned thereon. The InAs resonant tunneling layer has a plurality of quantized states which are misaligned with the ground state of the GaSb layer in a quiescent state, each of the quantized states of the InAs resonant tunneling layer are movable into alignment with the ground state of the GaSb layer to provide current flow through the transistor with the application of a specific potential to the terminal on the second InAs layer.

Abstract: A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

Abstract: A logic circuit including a pair of FETs connected in parallel and including first and second common current terminals, each of the FETs further having a control terminal connected to receive a logic signal thereon. A negative differential resistance device affixed to one of the first and second common current terminals and having a conductance characteristic such that the device operates at a peak current when one of the FETs is turned ON and at a valley current when both of the FETs are simultaneously turned ON. A load resistance coupled to the other of the first and second common current terminals and providing an output for the logic circuit.

Abstract: A bipolar heterojunction diode has an anode (11, 41), a blocking layer (12, 42) and a junction region (13, 14, 43). a heterojunction (32, 58) in the junction region (13, 14, 43) is utilized to create a misalignment between the band gap of the anode (11, 41) and a band gap of the heterojunction (13, 14, 43). The misalignment prevents a depletion region from extending into the heterojunction (13, 14, 43).