Abstract: An enhanced mobility semiconductor comprising a host quantum well having at least two charge carrier barrier layers of a wide bandgap material, each of the two charge carrier barrier layers being separated by a conducting region containing charge carriers is provided. A number of phonon barriers having a predetermined thickness are formed in the conducting region wherein the predetermined thickness is chosen to allow charge carrier tunneling through the phonon barriers.

Abstract: An enhanced conductivity structure comprising first and second coupled quantum well channel layers spaced from each other by a barrier layer of predetermined thickness is provided. The barrier layer and other supporting layers comprise a first material type, while the first and second quantum wells comprise a second material type having a narrower bandgap than the first material type. Each of the quantum wells is thin to confine current flow to the plane of the quantum wells. First and second spacer layers of the first material type are formed adjacent to each of the quantum wells, and planar doping layers are provided on each of the spacer layers. First and second buffer layers of the first material type are formed adjacent to each of the spacer layers.

Abstract: A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

Abstract: A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.

Abstract: A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel comprises a quantum well and at least one mono-atomic well or barrier layer is provided. The mono-atomic well or barrier layer has a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, an indium arsenide well monolayer is formed in an InGaAs channel region and functions to move a first quantized energy level E.sub.0 closer to the bottom of the channel region quantum well thereby increasing electron concentration by increasing effective band offset potential. Another embodiment uses an aluminum arsenide monolayer as a barrier monolayer in the InGaAs channel. By varying location of the monolayers, confinement of electrons in the channel can be improved.

Abstract: A superlattice structure comprising a host quantum well with a plurality of mini quantum wells formed therein is provided. The host quantum well has a confined energy state E.sub.2 which lies very near a lower band energy V.sub.1 of the host well, while each of the mini quantum wells has a single confined energy level E.sub.1 which lies below V.sub.1. Charge carriers are provided to the quantum well by doping material in the barrier layers to provide modulation doping of the quantum well. The mini quantum wells contain at least one monolayer of another material within their boundaries. The monolayer material is preferably electrically inactive and is a source of phonons which are generated for the purpose of charge carrier-phonon coupling in order to cause charge carrier pairing. In a preferred embodiment a transfer quantum well is formed between the barrier region of the host quantum well and the outermost mini quantum wells. The transfer quantum well has an energy state which couples to the E.sub.

Abstract: A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel is a top layer of a superlattice buffer, eliminating the need for a thick buffer layer. The superlattice buffer comprises alternating barrier and quantum well layers which are thin enough to provide wide separation in energy bands within the quantum wells. In a preferred embodiment the channel comprises a quantum well and one to five monolayers having a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, a ten period AlAs/GaAs superlattice is formed underneath the channel.

Abstract: An enhanced conductivity superlattice made from semiconductor materials provides enhanced conductivity. It is believed that conductivity can be enhanced sufficiently to produce superconductivity well above typical superconductivity temperatures of the semiconductor materials. The enhanced conductivity quantum well is a superlattice structure having a monolayer phonon generator sandwiched between layers of a host material. Barrier layers surround the host material to confine the host material electrons. In another embodiment, the monolayer may be located within the barrier layers. The monolayer generates phonons having an optical energy which is lower than the optical energy of the host material. The generated phonons couple with low energy electrons or holes to propagate without dissipation of electron energy.

Abstract: A cold cathode field emission device having a cone shaped emitter (112, 208) formed with a substantially normal (but not absolutely normal) vapor deposition process (109) wherein the substrate (101, 201) need not be rotated with respect to the vapor deposition target. The vapor deposition process forms an encapsulating layer (111, 207) that can either be utilized as an electrode within the completed device, or that can be removed to allow subsequent construction of additional layers.

Abstract: A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

Abstract: A quasi 1-dimensional electron gas transistor has been provided having a source electrode and a drain electrode. A plurality of electrodes are positioned between the source and drain electrodes in a manner which are parallel to the electron flow between the source and the drain electrodes. In one embodiment, the electrodes are interconnected by a gate electrode while in an alternate embodiment all the electrodes are connected to the source electrode and insulated from the gate electrode. This device provides a quantum wire for quasi 1-dimensional electron flow.

Abstract: An oxide passivated mesa epitaxial diode with an integral heat sink, and a process by which it may be fabricated. The passivation layer of highly pure thermally grown SiO.sub.2 is formed over the mesa walls in the region of the pn junction without causing a reaction between the contact metals and their surroundings during the high temperature environment imposed during thermal growth. The heat sink is deposited after the SiO.sub.2 passivation has been grown, replacing a polycrystalline silicon layer beneath the mesa formation which was used as a temporary structural support. Dopant, to form the pn junction, is introduced into the silicon wafer after the formation of the passivation layer but before the heat sink is deposited.

Abstract: An oxide passivated mesa epitaxial diode with an integral heat sink, and a process by which it may be fabricated. The passivation layer of highly pure thermally grown SiO.sub.2 is formed over the mesa walls in the region of the pn junction without causing a reaction between the contact metals and their surroundings during the high temperature environment imposed during thermal growth. The heat sink is deposited after the SiO.sub.2 passivation has been grown, replacing a polycrystalline silicon layer beneath the mesa formation which was used as a temporary structural support. Dopant, to form the pn junction, is introduced into the silicon wafer after the formation of the passivation layer but before the heat sink is deposited.

Abstract: A method is provided for fabricating a gridded Schottky barrier field effect transistor and to the transistor produced thereby. The transistor is constructed by means of a single high resolution mask which does not require alignment to any reference line. Utilizing the masking properties of an oxidation layer on the sides of the etched slots, platinum is deposited only at the bottom of the groove thereby eliminating the requirement of an additional photo-masking step or the necessity of subsequent removal of platinum from other surfaces of the wafer.