Patents by Inventor Herbert Palm
Herbert Palm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220391555Abstract: The present disclosure relates to multi-objective optimization of complex technical systems.Type: ApplicationFiled: May 26, 2022Publication date: December 8, 2022Applicant: paretos GmbHInventors: Herbert PALM, Fabian RANG, Thorsten HEILIG
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Patent number: 7184291Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.Type: GrantFiled: June 3, 2005Date of Patent: February 27, 2007Assignees: Infineon Technologies AG, Infineon Technologies Flash GmbH & Co. KGInventors: Michael Bollu, Armin Kohlhase, Christoph Ludwig, Herbert Palm, Josef Willer
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Patent number: 7159786Abstract: Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.Type: GrantFiled: August 23, 2004Date of Patent: January 9, 2007Assignee: Infineon Technologies AGInventors: Jurgen Fischer, Herbert Palm, Frank Puschner, Josef Willer
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Patent number: 7017821Abstract: An individual configuration contains at least a first structure and a second structure, which are aligned with respect to each other. A position sensing device that senses a relative position of the first structure with respect to the second structure, in order to establish that a manipulation has been performed on the configuration, is provided.Type: GrantFiled: September 24, 2002Date of Patent: March 28, 2006Assignee: Infineon Technologies AGInventors: Andreas Kux, Herbert Palm
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Publication number: 20050286296Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.Type: ApplicationFiled: June 3, 2005Publication date: December 29, 2005Inventors: Michael Bollu, Armin Kohlhase, Christoph Ludwig, Herbert Palm, Josef Willer
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Patent number: 6934854Abstract: The access time for the use of an electronic device, for example a chip, is prolonged after each unauthorized access attempt. The access time is determined by the time for the matching of the turn-on voltages of two floating gate cells. Before an access attempt, the turn-on voltage of one cell is set to a predefined initial value and the turn-on voltage of the other cell is set to a value which is higher in comparison and which is increased after each unauthorized access.Type: GrantFiled: March 1, 2002Date of Patent: August 23, 2005Assignee: Infineon Technologies AGInventors: Eric-Roger Brücklmeier, Herbert Palm, Andreas Kux
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Patent number: 6909294Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.Type: GrantFiled: August 11, 2003Date of Patent: June 21, 2005Assignee: Infineon Technologies AGInventors: Herbert Palm, Hans Taddiken, Erdmute Wohlrab
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Publication number: 20050116342Abstract: A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.Type: ApplicationFiled: December 28, 2004Publication date: June 2, 2005Inventors: Lawrence Clevenger, Ronald Filippi, Mark Hoinkis, Jeffery Hurd, Roy Iggulden, Herbert Palm, Hans Poetzlberger, Kenneth Rodbell, Florian Schnabel, Stefan Weber, Ebrahim Mehter
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Patent number: 6870263Abstract: A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.Type: GrantFiled: March 31, 1998Date of Patent: March 22, 2005Assignee: Infineon Technologies AGInventors: Lawrence A. Clevenger, Ronald G. Filippi, Mark Hoinkis, Jeffery L. Hurd, Roy C. Iggulden, Herbert Palm, Hans W. Poetzlberger, Kenneth P. Rodbell, Florian Schnabel, Stefan Weber, Ebrahim A. Mehter
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Publication number: 20050045730Abstract: Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.Type: ApplicationFiled: August 23, 2004Publication date: March 3, 2005Applicant: Infineon Technologies AGInventors: Jurgen Fischer, Herbert Palm, Frank Puschner, Josef Willer
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Patent number: 6844584Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.Type: GrantFiled: August 9, 2001Date of Patent: January 18, 2005Assignee: Infineon Technologies AGInventors: Herbert Palm, Josef Willer, Achim Gratz, Jakob Kriz, Mayk Roehrich
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Patent number: 6794249Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.Type: GrantFiled: February 28, 2003Date of Patent: September 21, 2004Assignee: Infineon Technologies AGInventors: Herbert Palm, Josef Willer
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Patent number: 6777725Abstract: An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array of memory cells allows to form the word line lithography on a perfect or almost perfect plane so that the word line formation results in a production with higher yield and, therefore, lower costs for the individual integrated memory circuit.Type: GrantFiled: June 14, 2002Date of Patent: August 17, 2004Assignee: Ingentix GmbH & Co. KGInventors: Josef Willer, Herbert Palm
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Publication number: 20040032244Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.Type: ApplicationFiled: August 11, 2003Publication date: February 19, 2004Inventors: Herbert Palm, Hans Taddiken, Erdmute Wohlrab
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Publication number: 20030230783Abstract: An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array of memory cells allows to form the word line lithography on a perfect or almost perfect plane so that the word line formation results in a production with higher yield and, therefore, lower costs for the individual integrated memory circuit.Type: ApplicationFiled: June 14, 2002Publication date: December 18, 2003Inventors: Josef Willer, Herbert Palm
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Publication number: 20030151091Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W. .Type: ApplicationFiled: February 28, 2003Publication date: August 14, 2003Applicant: Infineon Technologies AGInventors: Herbert Palm, Josef Willer
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Patent number: 6601202Abstract: A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At least one sub-set of the connections is in the form of a respective interlocking element which can be switched through an activation line (Scan Enable) from a normal mode to a test mode and which has a further data input and data output. The further data inputs and outputs are connected to one another by data line sections in such a manner that the interlocking elements form a shift register which provides a scan path. At least one electrically programmable protection element, which either interrupts a given line or connects it to a defined potential, is disposed along the activation line (Scan Enable) and/or the data line sections.Type: GrantFiled: March 28, 2001Date of Patent: July 29, 2003Assignee: Infineon Technologies AGInventors: Herbert Palm, Michael Smola, Stefan Wallstab
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Patent number: 6548861Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.Type: GrantFiled: July 6, 2001Date of Patent: April 15, 2003Assignee: Infineon Technologies AGInventors: Herbert Palm, Josef Willer
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Publication number: 20030065473Abstract: An individual configuration contains at least a first structure and a second structure, which are aligned with respect to each other. A position sensing device that senses a relative position of the first structure with respect to the second structure, in order to establish that a manipulation has been performed on the configuration, is provided.Type: ApplicationFiled: September 24, 2002Publication date: April 3, 2003Inventors: Andreas Kux, Herbert Palm
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Publication number: 20030015752Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.Type: ApplicationFiled: August 9, 2001Publication date: January 23, 2003Applicant: Infineon Technologies AGInventors: Herbert Palm, Josef Willer, Achim Gratz, Jakob Kriz, Mayk Roehrich