Abstract: An electrically conductive layer (8) or layer sequence, in particular a metal silicide or a polysilicon layer (14) with a metal-containing layer (15) applied to it, reducing the resistance of the buried bit lines, which layer or layer sequence has been patterned in strip form so as to correspond to the bit lines, is arranged on the source/drain regions (3, 4) of memory transistors with an ONO memory layer sequence (5, 6, 7) and gate electrodes (2) arranged in trenches. The metal silicide is preferably cobalt silicide; the metal-containing layer is preferably tungsten silicide or WN/W.

Abstract: The access time for the use of an electronic device, for example a chip, is prolonged after each unauthorized access attempt. The access time is determined by the time for the matching of the turn-on voltages of two floating gate cells. Before an access attempt, the turn-on voltage of one cell is set to a predefined initial value and the turn-on voltage of the other cell is set to a value which is higher in comparison and which is increased after each unauthorized access.

Abstract: The power supply device has a temporary energy store, a main energy store, and a switching device. The switching device has three switching states. The temporary energy store is connected in the first switching state to a power supply input and is connected in the second switching state to the main energy store, which is connected to a power supply output. An energy discharge device is connected to the temporary energy store in the third switching state of the switching device which follows directly the second switching state.

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body with a gate electrode (2) which is arranged in a trench between a source region (3) and a drain region (4), which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode there is an oxide-nitride-oxide layer sequence (5, 6, 7), which is provided for the purpose of trapping charge carriers at source and drain.

Abstract: A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At least one sub-set of the connections is in the form of a respective interlocking element which can be switched through an activation line (Scan Enable) from a normal mode to a test mode and which has a further data input and data output. The further data inputs and outputs are connected to one another by data line sections in such a manner that the interlocking elements form a shift register which provides a scan path. At least one electrically programmable protection element, which either interrupts a given line or connects it to a defined potential, is disposed along the activation line (Scan Enable) and/or the data line sections.

Abstract: The power supply device has a temporary energy store, a main energy store, and a switching device. The switching device has three switching states. The temporary energy store is connected in the first switching state to a power supply input and is connected in the second switching state to the main energy store, which is connected to a power supply output. An energy discharge device is connected to the temporary energy store in the third switching state of the switching device which follows directly the second switching state.

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Abstract: A method of forming aluminum contacts of submicron dimensions wherein, after formation of both vias and line openings in a silicon oxide layer, a metal stop layer is deposited, followed by deposition of aluminum. Alternatively, the metal stop layer is deposited prior to forming the vias and line openings. The excess aluminum is removed by chemical-mechanical polishing, the stop layer providing high selectivity to the chemical mechanical polishing. The stop layer is then removed. The resultant silicon oxide-aluminum surface is planar and undamaged by the chemical-mechanical polishing step.

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.