Abstract: A method and a system for providing fusing after packaging of semiconductor devices are disclosed. In one embodiment, a semiconductor device is provided comprising a substrate comprising a fuse area, at least one fuse disposed in the fuse area, and at least one layer disposed over the substrate, wherein the at least one layer comprises at least one opening exposing the at least one fuse.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A method and a system for providing fusing after packaging of semiconductor devices are disclosed. In one embodiment, a semiconductor device is provided comprising a substrate comprising a fuse area, at least one fuse disposed in the fuse area, and at least one layer disposed over the substrate, wherein the at least one layer comprises at least one opening exposing the at least one fuse.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: A method replaces a controller, particularly a faulty and/or outmoded controller, in an onboard power supply system in a vehicle. The controller to be replaced is replaced by a functional and/or new controller. The controller to be replaced and the new controller are operated by incompatible operating software. In the method at least one software component is exported from a software development environment for the operating software of the controller to be replaced by a data processing apparatus. The software component is converted into a code, which can be imported into a software development environment for the operating software of the functional and/or new controller, by the data processing apparatus. The code is imported into the software development environment of the operating software of the functional and/or new controller by the data processing apparatus. The operating software for the new controller is produced on the basis of the imported code.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract: The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract: The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.