Patents by Inventor Herbert Schaefer
Herbert Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7449389Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.Type: GrantFiled: October 27, 2006Date of Patent: November 11, 2008Assignee: Infineon Technologies AGInventors: Thomas Meister, Herbert Schäfer, Josef Böck, Rudolf Lachner
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Patent number: 7371650Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.Type: GrantFiled: October 24, 2003Date of Patent: May 13, 2008Assignee: Infineon Technologies AGInventors: Josef Böck, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schäfer, Martin Seck
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Publication number: 20080067627Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.Type: ApplicationFiled: September 13, 2007Publication date: March 20, 2008Inventors: Josef Boeck, Herbert Knapp, Wolfgang Liebl, Herbert Schaefer
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Publication number: 20070222032Abstract: A bipolar transistor has a base, an emitter and an emitter contact. The emitter has a monocrystalline layer and a polycrystalline layer, which are disposed between the base and the emitter contact in the mentioned order.Type: ApplicationFiled: March 9, 2007Publication date: September 27, 2007Applicant: Infineon Technologies AGInventors: Herbert Schaefer, Josef Boeck, Rudolf Lachner, Thomas Meister
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Patent number: 7256472Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.Type: GrantFiled: July 11, 2003Date of Patent: August 14, 2007Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schäfer
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Patent number: 7135757Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.Type: GrantFiled: August 4, 2004Date of Patent: November 14, 2006Assignee: Infineon Technologies AGInventors: Reinhard Stengl, Thomas Meister, Herbert Schäfer, Martin Franosch
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Patent number: 7064360Abstract: A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.Type: GrantFiled: February 4, 2002Date of Patent: June 20, 2006Assignee: Infineon Technologies AGInventors: Martin Franosch, Thomas Meister, Herbert Schaefer, Reinhard Stengl
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Patent number: 6995416Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.Type: GrantFiled: May 26, 2004Date of Patent: February 7, 2006Assignee: Infineon Technologies AGInventors: Hans Reisinger, Reinhard Stengl, Herbert Schäfer
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Patent number: 6909141Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.Type: GrantFiled: January 16, 2002Date of Patent: June 21, 2005Assignee: Infineon Technologies AGInventors: Wolfgang Rösner, Thomas Schulz, Lothar Risch, Thomas Äugle, Herbert Schäfer, Martin Franosch
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Patent number: 6867105Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.Type: GrantFiled: August 8, 2002Date of Patent: March 15, 2005Assignee: Infineon Technologies AGInventors: Reinhard Stengl, Thomas Meister, Herbert Schäfer, Martin Franosch
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Publication number: 20040099881Abstract: The method according to the invention makes it possible to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.Type: ApplicationFiled: December 22, 2003Publication date: May 27, 2004Inventors: Martin Franosch, Thomas Meister, Herbert Schaefer, Reinhard Stengl
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Patent number: 6635545Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.Type: GrantFiled: June 3, 2002Date of Patent: October 21, 2003Assignee: Infineon Technologies AGInventors: Josef Böck, Wolfgang Klein, Herbert Schäfer, Martin Franosch, Thomas Meister, Reinhard Stengl
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Patent number: 6600200Abstract: A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.Type: GrantFiled: August 25, 2000Date of Patent: July 29, 2003Assignee: Infineon Technologies AGInventors: Bernhard Lustig, Herbert Schäfer, Lothar Risch
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Patent number: 6552385Abstract: A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.Type: GrantFiled: January 8, 2001Date of Patent: April 22, 2003Assignee: Infineon Technologies AGInventors: Gerhard Beitel, Martin Franosch, Thomas Peter Haneder, Gerrit Lange, Hans Reisinger, Herbert Schäfer, Stephan Schlamminger, Hermann Wendt
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Patent number: 6548846Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.Type: GrantFiled: December 11, 2000Date of Patent: April 15, 2003Assignee: Infineon Technologies AGInventors: Hans Reisinger, Volker Lehmann, Reinhard Stengl, Hermann Wendt, Gerrit Lange, Harald Bachhofer, Martin Franosch, Herbert Schäfer
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Patent number: 6215140Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.Type: GrantFiled: September 20, 1999Date of Patent: April 10, 2001Assignee: Siemens AktiengesellschaftInventors: Hans Reisinger, Martin Franosch, Herbert Schäfer, Reinhard Stengl, Volker Lehmann, Gerrit Lange, Hermann Wendt
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Patent number: 6204119Abstract: A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.Type: GrantFiled: May 14, 1999Date of Patent: March 20, 2001Assignee: Siemens AktiengesellschaftInventors: Gerrit Lange, Martin Franosch, Wolfgang Hönlein, Volker Lehmann, Hans Reisinger, Herbert Schäfer, Reinhard Stengl, Hermann Wendt
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Patent number: 6194765Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.Type: GrantFiled: May 17, 1999Date of Patent: February 27, 2001Assignee: Siemens AktiengesellschaftInventors: Hans Reisinger, Reinhard Stengl, Ulrike Grüning, Volker Lehmann, Hermann Wendt, Josef Willer, Martin Franosch, Herbert Schäfer
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Patent number: 6022786Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).Type: GrantFiled: February 27, 1998Date of Patent: February 8, 2000Assignee: Siemens AktiengesellschaftInventors: Martin Franosch, Wolfgang Hoenlein, Helmut Klose, Gerrit Lange, Volker Lehmann, Hans Reisinger, Herbert Schaefer, Reinhard Stengl, Hermann Wendt, Dietrich Widmann
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Patent number: 6018174Abstract: A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.Type: GrantFiled: June 26, 1998Date of Patent: January 25, 2000Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Martin Schrems, Jack Mandelman, Joachim Hoepfner, Herbert Schaefer, Reinhard Stengl