Abstract: A method for protecting an integrated circuit against unauthorized access to key registers, wherein functions and/or applications of the integrated circuit are unlocked and/or activated via data stored in key registers, such as during the start-up of the integrated circuit and/or during ongoing operation, where if such a key register is accessed, the data word used to perform the access is compared with specified key data, and if access via a data word deviating from the specified key data is detected, the access is marked as unauthorized, the access marked as unauthorized is then recorded and evaluated, and after the analysis, appropriate protective measures are triggered to prevent further unauthorized access such that a key register method for protecting sensitive data is expanded in a simple manner and hacker attacks are quickly detected and thwarted.

Abstract: A circuit arrangement and method for temporally limiting and separating access between at least one master unit and at least one slave unit via a network-on-a-chip bus system in a system-on-a-chip, wherein the access between the at least one master and slave units is implemented via communication paths defined by bus interfaces, where within the circuit arrangement, the network-on-a-chip bus system is expanded by an adaptation unit that includes an access manager and a complementary logic for the bus interfaces, where the adaptation unit and the bus interfaces are then controlled by the access manager via the complementary logic using a communication plan such that access between the master and slave units via the communication paths specified by bus interfaces is performed in accordance with the temporal requirements of the communication plan so that time-controlled systems can be implemented simply using commercially obtainable standard bus systems.

Abstract: A circuit arrangement and method for accessing slave units in a system on chip in a controlled manner, wherein an access of a master unit of the system on chip to one of the slave units is performed via a network-on-chip bus system using an access address, where a memory protection unit is integrated between the at least one master unit and the network-on-chip bus system, and access authorization of the master unit to a slave unit is checked by the memory protection unit by comparing the access address with specified address sections, and when an unauthorized access of the master unit to a slave unit is identified, the access address is modified by the memory protection unit such that the unauthorized access is terminated in the network-on-chip bus system.

Abstract: In an application-specific integrated circuit (ASIC), a description of the logic circuit is formulated in a hardware description language and then converted into a description of a corresponding physical circuit, i.e., into a netlist, using a conversion program, i.e., a synthesis tool. The description at least largely consisting of standard cells. During the conversion process, the standard cells which are used in the netlist are replaced with standard cell versions which have a correspondingly balanced power dissipation. Spying on a mode of operation of the circuit by analyzing a power consumption of the circuit is thus advantageously hindered or prevented, in particular in security-relevant circuits.

Abstract: According to the invention, the aim of an optimisation of the timing in normal mode with no disadvantage to, or limitation of the scanning mode may be achieved for an electronic component with an integrated circuit comprising output flip-flops, the output data of which in the normal mode of the component is transmitted to an output buffer on the component, controlled by a control signal, the control signal being provided in normal mode by an output-enable flip-flop provided for the output buffer and in a scan mode for the component by scan-enable cells. Said aim is achieved, whereby a device is provided, in which in the scan mode, a scan-enable cell controls at least two output buffers.

Abstract: With methods for developing an electronic component, in which a layout is executed for a component and a file is also generated with timing information, the present invention avoids the superfluous net list changes by providing the following steps: a) Executing an initial timing analysis using the file to identify violations of timing requirements; b) Producing the chip in accordance with the current layout, if no timing violations were detected, otherwise c) Saving information about violations of the timing requirements identified in at least one patch list; d) Changing the file in accordance with the violation information in the patch list; e) Executing the timing analysis again using the modified file; f) Iteration of Steps c), d) and e), if a new timing violation was established; g) When no more timing violations are established, executing a layout adaptation step and generating a new file containing runtime information based on the adapted layout; and h) Returning to Step a) and executing the step.

Abstract: A method for testing an emulated logic circuit is described wherein a model of the logic circuit is loaded into a hardware emulator (EM) and there put into an operating mode in which flip-flops it contains are functionally chained into one or more shift registers. The structural arrangement of the logic circuit in the hardware emulator (EM) is subsequently compared with the structural arrangement of the model of the logic circuit with the assistance of this operating mode. A device for implementing the method is also described.

Abstract: A component with integrated circuits combined into functional blocks, in which case the functional blocks have connections between them and a relevant residual logic. The residual logic of the functional blocks is first tested by entering test data into the residual logic and a first signature is output for each block, and then the connections between the blocks are tested by transferring test data via the connections and a second signature is output.