Patents by Inventor Hermann Wendt
Hermann Wendt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10157765Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.Type: GrantFiled: November 23, 2016Date of Patent: December 18, 2018Assignee: Infineon Technologies AGInventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
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Patent number: 9959890Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL. The second etching process can also etch a portion of the magnetoresistive stack. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.Type: GrantFiled: January 6, 2017Date of Patent: May 1, 2018Assignee: Infineon Technologies AGInventors: Wolfgang Raberg, Andreas Strasser, Hermann Wendt, Klemens Pruegl
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Patent number: 9780161Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.Type: GrantFiled: August 27, 2015Date of Patent: October 3, 2017Assignee: Infineon Technologies AGInventors: Markus Menath, Thomas Fischer, Hermann Wendt
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Publication number: 20170125044Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL. The second etching process can also etch a portion of the magnetoresistive stack. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.Type: ApplicationFiled: January 6, 2017Publication date: May 4, 2017Applicant: Infineon Technologies AGInventors: Wolfgang Raberg, Andreas Strasser, Hermann Wendt, Klemens Pruegl
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Publication number: 20170076970Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.Type: ApplicationFiled: November 23, 2016Publication date: March 16, 2017Inventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
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Patent number: 9570099Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL and a portion of the magnetoresistive stack. The method can further include depositing a photoresist layer on the hard mask before the first etching process and removing the photoresist layer from the hard mask following the first etching process. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.Type: GrantFiled: May 20, 2015Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Wolfgang Raberg, Andreas Strasser, Hermann Wendt, Klemens Pruegl
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Publication number: 20160343392Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL and a portion of the magnetoresistive stack. The method can further include depositing a photoresist layer on the hard mask before the first etching process and removing the photoresist layer from the hard mask following the first etching process. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.Type: ApplicationFiled: May 20, 2015Publication date: November 24, 2016Inventors: Wolfgang Raberg, Andreas Strasser, Hermann Wendt, Klemens Pruegl
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Patent number: 9401322Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: July 25, 2011Date of Patent: July 26, 2016Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 9293371Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: GrantFiled: June 24, 2015Date of Patent: March 22, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Anja Reitmeier, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Publication number: 20150372073Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.Type: ApplicationFiled: August 27, 2015Publication date: December 24, 2015Inventors: Markus Menath, Thomas Fischer, Hermann Wendt
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Patent number: 9183977Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.Type: GrantFiled: April 20, 2012Date of Patent: November 10, 2015Assignee: Infineon Technologies AGInventors: Markus Menath, Thomas Fischer, Hermann Wendt
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Publication number: 20150294911Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: ApplicationFiled: June 24, 2015Publication date: October 15, 2015Inventors: Anja Reitmeier, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Patent number: 9093385Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: GrantFiled: May 28, 2013Date of Patent: July 28, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Publication number: 20150147850Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: Infineon Technologies AGInventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
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Publication number: 20150084196Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: ApplicationFiled: October 6, 2014Publication date: March 26, 2015Inventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Publication number: 20140357055Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: Infineon Technologies AGInventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Patent number: 8860225Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.Type: GrantFiled: October 12, 2011Date of Patent: October 14, 2014Assignee: Infineon Technologies AGInventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
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Patent number: 8637967Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.Type: GrantFiled: November 15, 2010Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Markus Menath, Hermann Wendt, Berthold Schuderer
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Patent number: 8610238Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.Type: GrantFiled: December 8, 2010Date of Patent: December 17, 2013Assignee: Infineon Technologies AGInventors: Erdem Kaltalioglu, Hermann Wendt
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Publication number: 20130277797Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Markus Menath, Thomas Fischer, Hermann Wendt