Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

Abstract: A method for producing an Al-containing layer having a planar surface onto a substrate having hole structures with high aspect ratios formed in the surface of the substrate, wherein the Al-containing layer is applied in a sputtering process during which the substrate is held at an elevated temperature and the sputtering process is implemented at a pressure between 1.3.times.10.sup.-2 Pa and 13 Pa and at a low partial gas pressure. The substrate can be held at a temperature between approximately 400.degree. C. and 500.degree. C. during the sputtering process. A partial residual gas pressure of less than 1.3.times.10.sup.-5 PA can prevail in the vacuum. An intermediate layer of pure titanium and a barrier layer of TiN can be directly deposited onto the substrate and the Al-containing layer can then be applied onto this intermediate end barrier layer.

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Abstract: An apparatus for the chemical-mechanical polishing of wafers has a rotating disk provided with a polishing body, a supply device for a polishing fluid and a holding device for the wafer. An axis of the disk runs parallel to the surface of the wafer. A cylindrical edge surface of the disk is provided with the polishing body in such a way that a trench with a specific cross section can be made in the wafer.

Abstract: For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.

Abstract: To produce a silicon capacitor, hole apertures at whose surface a conductive zone (40) is formed by doping and whose surface is provided with a dielectric layer (6) and a conductive layer (7) are generated in an n-doped silicon substrate (1). To compensate for mechanical strains in the silicon substrate (1) brought about by the doping of the conductive zone (40), the conductive zone (40) is additionally doped with germanium which is outdiffused from a germanium-doped layer.

Abstract: Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively etched with respect to the first material. Layered structures are formed from the sequence of layers, with the flanks of the layered structures each having a conductive support structure. The layered structures are formed with openings, such as gaps, in which the surface of the layers is exposed. The layers made of the second material are selectively removed with respect to the layers made of the first material. The exposed surface of the layers made of the first material and of the support structure are provided with a capacitor dielectric, onto which a counter-electrode is placed. The capacitor is made by etching p.sup.- -doped polysilicon that is selective to p.sup.+ -doped polysilicon.

Abstract: For manufacturing a silicon capacitor, hole openings are produced in an n-doped silicon substrate, a p.sup.+ -doped region is formed at the surface thereof and this surface is provided with a dielectric layer together with a conductive layer. The silicon substrate is thinned with an etching proceeding from the back side, this etching attacking silicon selectively to p.sup.+ -doped silicon and therefore stopping when the p.sup.+ -doped region is reached.

Abstract: For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).

Abstract: A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.

Abstract: A bipolar transistor with a collector, a base and an emitter disposed in vertical succession includes a semiconductor substrate, insulating oxide zones disposed in the substrate for separating adjacent transistors, and a buried collector terminal layer at least partly disposed on the insulating oxide zones. An insulator structure laterally surrounding a collector. A subcollector is surrounded by the insulating oxide zones, has the same conductivity type with a lower impedance than the collector, is disposed under the collector and under the insulator structure, and is electrically connected to the collector. The insulator structure covers the buried collector terminal layer, laterally insulates the collector from the buried collector terminal layer, and has lateral surfaces extending inside the insulating oxide regions up to the subcollector. The buried collector terminal layer is in direct contact with the subcollector.