Abstract: Systems, methods, and apparatus related to memory devices that use multi-pillar memory cells for performing multiplication and other operations. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. The memory cells are arranged in pillars of memory cells connected in series. Each memory cell uses at least one transistor from two or more different pillars. A bitline is formed overlying the pillars. The bitline is electrically connected to the pillars and accumulates output currents from the pillars when performing the matrix vector multiplication.

Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a digit line and an access line of a number of access lines. A number of signals corresponding to bits of a second number may be driven on the number of access lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a first integrated circuit die has a memory cell array. The memory cell array includes memory cells programmable to store weights (e.g., representing synapses of a neural network). A second integrated circuit die has logic circuitry that performs multiplication of the stored weights by an input pattern. The second die is connected to the first die by hybrid bonding. Multiplication results are determined by the logic circuitry based on accumulation of output currents from at least a portion of the memory cells.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logic states of memory cells. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply different voltages to the memory cells during multiplication. The magnitudes of the different voltages correspond to a significance of the bit stored by the respective memory cell. One or more inputs are applied to the memory cells to multiply the inputs by the multi-bit weight. Output currents from the memory cells are summed on a common line. The sum of the output currents is used to provide at least one result from the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multi-bit to multi-bit multiplication using sets of memory cells. In one approach, a memory cell array has sets of memory cells. Each set is programmable to store a multi-bit signed weight. Voltage drivers apply voltages to each set. The voltages correspond to multi-bit signed inputs. One or more common lines are coupled to each set for summing output currents from the sets during the multiplication. A digitizer provides signed results based on summing the output currents. The signed results are added with adjustment for the bit significance of each signed result to provide a final accumulation result for the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells programmed to have different thresholds based on bit significance. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply voltages to the memory cells. The applied voltages represent inputs to be multiplied by the weights. A common line is coupled each of the memory cells to accumulate output currents from the cells. The output currents each have a magnitude corresponding to the significance of the bit stored by the respective memory cell. A digitizer uses the summed output currents as an input and provides a digital result as an output.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using sets each containing two memory cells. In one approach, sets organized as pairs of memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells at first and second times. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are accumulated at the first and second times in a respective common line for each set. A signed result for each set is provided based on digitizing sums of the output currents accumulated at the first and second times.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of four memory cells. In one approach, memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are summed in first and second lines. A sum of the output currents in each line is digitized to provide first and second results. The first and second results are combined to provide a signed result for each set.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of memory cells. In one approach, memory cells in the sets are programmed so that each set stores a signed weight. Voltage drivers apply voltages to the memory cells in each set. The voltages correspond to signed inputs to multiply by the signed weights in the sets. One or more common lines (e.g., bitlines) are coupled to each set for summing output currents from the sets. A digitizer provides a signed result based on summing the output currents from the sets.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. In one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or ?1). Voltages that represent signed inputs (e.g., +1, 0, or ?1) are applied to the memory cells to perform the multiplication. A result from the multiplication is determined based on summing of output currents from the memory cells.

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.