Patents by Inventor Hernan A. Castro

Hernan A. Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device architecture
    Patent number: 10497435
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everado Torres Flores, Jeremy M. Hirst
  • OPERATIONAL SIGNALS GENERATED FROM CAPACITIVE STORED CHARGE
    Publication number: 20190362788
    Abstract: Methods, a memory device, and a system are disclosed. One such method includes providing a first pulse to one of multiple bit lines of a variable resistance memory structure at a first time using a first transistor, a second pulse to the one of the multiple bit lines at a second time later than the first time using the first transistor, and a third pulse to the one of the multiple bit lines at a third time later than the second time using a second transistor.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric S. Carman
  • Apparatuses and methods for bi-directional access of cross-point arrays
    Patent number: 10482956
    Abstract: The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
    Publication number: 20190341102
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 7, 2019
    Inventor: Hernan A. Castro
  • OPERATIONS ON MEMORY CELLS
    Publication number: 20190341112
    Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventor: Hernan A. Castro
  • COMPARING INPUT DATA TO STORED DATA
    Publication number: 20190333577
    Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.
    Type: Application
    Filed: July 12, 2019
    Publication date: October 31, 2019
    Inventor: Hernan A. Castro
  • Apparatuses and methods for efficient write in a cross-point array
    Patent number: 10460802
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Ovonyx Memory Technology, LLC
    Inventor: Hernan Castro
  • CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES
    Publication number: 20190326356
    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Hernan A. Castro, Stephen H. Tang, Stephen W. Russell
  • CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES
    Publication number: 20190326357
    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Hernan A. Castro, Stephen H. Tang, Stephen W. Russell
  • BURIED LINES AND RELATED FABRICATION TECHNIQUES
    Publication number: 20190327835
    Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Hernan A. Castro, Stephen W. Russell, Stephen H. Tang
  • Apparatuses for modulating threshold voltages of memory cells
    Patent number: 10431270
    Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Operational signals generated from capacitive stored charge
    Patent number: 10424371
    Abstract: Methods, a memory device, and a system are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric S. Carman
  • Pulsed integrator and memory techniques
    Patent number: 10410721
    Abstract: Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Jeremy M. Hirst
  • Operations on memory cells
    Patent number: 10395738
    Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Memory tile access and selection patterns
    Patent number: 10387338
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Comparing input data to stored data
    Patent number: 10366747
    Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Accessing memory cells in parallel in a cross-point array
    Patent number: 10360975
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • COMPARING INPUT DATA TO STORED DATA
    Publication number: 20190164600
    Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response an applied voltage differential across the memory cell.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventor: Hernan A. Castro
  • OPERATIONS ON MEMORY CELLS
    Publication number: 20190164611
    Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventor: Hernan A. Castro
  • PULSED INTEGRATOR AND MEMORY TECHNIQUES
    Publication number: 20190156887
    Abstract: Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Inventors: Hernan A. Castro, Jeremy M. Hirst