Patents by Inventor Hideaki Aochi

Hideaki Aochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446249
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10446212
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Susumu Hashimoto, Yasuaki Ootera, Tsuyoshi Kondo, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Nobuyuki Umetsu, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu, Yuichi Ito
  • Publication number: 20190287598
    Abstract: According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.
    Type: Application
    Filed: September 12, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya SHIMADA, Yasuaki OOTERA, Tsuyoshi KONDO, Nobuyuki UMETSU, Michael Arnaud QUINSAT, Masaki KADO, Susumu HASHIMOTO, Shiho NAKAMURA, Hideaki AOCHI, Tomoya SANUKI, Shinji MIYANO, Yoshihiro UEDA, Yuichi ITO, Yasuhito YOSHIMIZU
  • Publication number: 20190287637
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Myano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10418378
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Publication number: 20190273090
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: September 5, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • Patent number: 10403635
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 10403381
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Takuya Shimada, Susumu Hashimoto, Nobuyuki Umetsu, Yasuaki Ootera, Masaki Kado, Tsuyoshi Kondo, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10354739
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10311932
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuyuki Umetsu, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10304902
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaki Kado, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Nobuyuki Umetsu, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Publication number: 20190148404
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaru KITO, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20190096908
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Publication number: 20190088345
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Michael Arnaud QUINSAT, Takuya SHIMADA, Susumu HASHIMOTO, Nobuyuki UMETSU, Yasuaki OOTERA, Masaki KADO, Tsuyoshi KONDO, Shiho NAKAMURA, Tomoya SANUKI, Yoshihiro UEDA, Yuichi ITO, Shinji MIYANO, Hideaki AOCHI, Yasuhito YOSHIMIZU
  • Publication number: 20190088346
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Application
    Filed: March 13, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Publication number: 20190088712
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaki KADO, Tsuyoshi KONDO, Yasuaki OOTERA, Takuya SHIMADA, Michael Arnaud QUINSAT, Nobuyuki UMETSU, Susumu HASHIMOTO, Shiho NAKAMURA, Hideaki AOCHI, Tomoya SANUKI, Shinji MIYANO, Yoshihiro UEDA, Yuichi ITO, Yasuhito YOSHIMIZU
  • Publication number: 20190088304
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Susumu HASHIMOTO, Yasuaki Ootera, Tsuyoshi Kondo, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Nobuyuki Umetsu, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu, Yuichi Ito
  • Patent number: 10211219
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20190027494
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Publication number: 20180374864
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: September 4, 2018
    Publication date: December 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi