Patents by Inventor Hideaki Arima
Hideaki Arima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9202541Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.Type: GrantFiled: September 7, 2012Date of Patent: December 1, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shuuichi Senou, Kenjyu Shimogawa, Susumu Takano, Toshihiko Funaki, Hideaki Arima
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Patent number: 8759891Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface formed on a major surface of a semiconductor substrate to extend from a memory cell region to a peripheral circuit region thereof. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top and bottom surfaces of the capacitor lower electrode part.Type: GrantFiled: January 25, 2013Date of Patent: June 24, 2014Assignee: Renesas Electronics CorporationInventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 8471321Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: September 13, 2010Date of Patent: June 25, 2013Assignee: Renesas Electronics CorporationInventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Publication number: 20130058173Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.Type: ApplicationFiled: September 7, 2012Publication date: March 7, 2013Inventors: Shuuichi SENOU, Kenjyu Shimogawa, Susumu Takano, Toshihiko Funaki, Hideaki Arima
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Semiconductor device, and failure detection system and failure detection method of data hold circuit
Patent number: 8362799Abstract: A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.Type: GrantFiled: March 28, 2011Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventor: Hideaki Arima -
Semiconductor device, and failure detection system and failure detection method of data hold circuit
Publication number: 20110241724Abstract: A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.Type: ApplicationFiled: March 28, 2011Publication date: October 6, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hideaki Arima -
Publication number: 20110001177Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: ApplicationFiled: September 13, 2010Publication date: January 6, 2011Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori TANAKA, Masahiro Shimizu, Hideaki Arima
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Patent number: 7816204Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: May 23, 2008Date of Patent: October 19, 2010Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7795648Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: February 10, 2009Date of Patent: September 14, 2010Assignee: Renesas Technology CorporationInventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7782700Abstract: In a semiconductor or memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and the first ODT circuit, and detects a level of a voltage applied to the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.Type: GrantFiled: April 8, 2009Date of Patent: August 24, 2010Assignee: NEC Electronics CorporationInventors: Kenichi Kuboyama, Hideaki Arima
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Patent number: 7754562Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: February 10, 2009Date of Patent: July 13, 2010Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Publication number: 20090256587Abstract: In a semiconductor memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.Type: ApplicationFiled: April 8, 2009Publication date: October 15, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Kenichi Kuboyama, Hideaki Arima
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Publication number: 20090254784Abstract: A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output port. The ODT circuit is provided between the data input-output port and a termination port. The JTAG circuit controls the ODT circuit in response to an instruction such that the data input-output port and the termination port are electrically connected with each other.Type: ApplicationFiled: April 8, 2009Publication date: October 8, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: MASATOSHI SONODA, YUUJIROU SHIMIZU, HIDEAKI ARIMA
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Publication number: 20090184354Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: ApplicationFiled: February 10, 2009Publication date: July 23, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori TANAKA, Masahiro Shimizu, Hideaki Arima
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Publication number: 20090148989Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: ApplicationFiled: February 10, 2009Publication date: June 11, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori TANAKA, Masahiro SHIMIZU, Hideaki ARIMA
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Patent number: 7439132Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: January 23, 2006Date of Patent: October 21, 2008Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Publication number: 20080233707Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: ApplicationFiled: May 23, 2008Publication date: September 25, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7368776Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: January 23, 2006Date of Patent: May 6, 2008Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Publication number: 20060128095Abstract: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: ApplicationFiled: January 23, 2006Publication date: June 15, 2006Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Publication number: 20060113579Abstract: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: ApplicationFiled: January 23, 2006Publication date: June 1, 2006Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima