Abstract: An MIS-type semiconductor device comprises PSD structure and LDD structure. The LDD structure comprises high concentration impurity regions formed by thermally diffusing impurities which have been contained in source/drain electrode conductive layers made of polysilicon onto a semiconductor substrate, and low concentration impurity regions formed through ion implantation using resist patterned on channel regions and the source/drain electrode conductive layers as mask. A gate electrode is formed, after formation of the low concentration impurity regions, to cover them and have its edges overlap the source/drain electrode conductive layers. The LDD structure suppresses the short channel effects which might be caused in the MIS-type semiconductor device and thus enables channels length to be miniaturized while the PSD structure enables also miniaturization of source/drain structure.

Abstract: First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region.

Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Abstract: Here is disclosed an improved polysilicon pad LOCOS method. An underlying oxide film is formed on a main surface of a semiconductor substrate. Over the underlying oxide film, polysilicon to be a field oxide film is then deposited. Subsequently, a nitride film is formed on the polysilicon. Thereafter, the nitride film is patterned to leave patterns of a predetermined configuration in an area to be a device region. Using the patterned nitride film as a mask, the polysilicon other than a portion beneath the mask is thermally oxidized to form a field oxide film on the main surface of the semiconductor substrate. The nitride film having served as a mask is then removed to expose the unoxidized polysilicon remaining under the mask. Subsequently, the unoxidized polysilicon is etched away under predetermined conditions which do not allow any etching of the underlying oxide film.

Abstract: In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

Abstract: An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a second refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.

Abstract: An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced against from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.

Abstract: A memory cell of 1 bit is constituted by 1 selecting transistor and 1 memory transistor in an EEPROM. One of the source-drain regions is commonly used by the selecting transistor and the memory transistor. The commonly used source-drain region is manufactured through the following steps. First, a gate electrode of the transistor is formed. An oxide film is deposited on the entire surface. A resist is applied thereon and is etched back to expose a surface of the oxide film on the gate electrode. Thereafter, the oxide films deposited on the side surfaces of the gate electrode are removed to form opening portions. Impurities are implanted to the silicon substrate utilizing the opening portions.

Abstract: First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region.

Abstract: An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced apart from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.

Abstract: A sense transistor of an EEPROM has a conductive diffusion layer which is isolated from the source-drain region of the sense transistor and newly formed on the surface of the semiconductor substrate beneath the floating gate of the sense transistor. The conductive diffusion layer is connected to the control gate of the sense transistor, whereby a capacitance between the control gate and the floating gate is increased without increasing the facing area of the control gate and the floating gate.

Abstract: In a surface region of a silicon semiconductor substrate (10), an arsenic diffusion layer (20) having a surface arsenic concentration of 5.times.10.sup.18 cm.sup.-3 to 5.times.10.sup.19 cm.sup.-3 is formed and then, the arsenic diffusion layer (20) is oxidized by a thermal oxidation method so that a thermally oxidized film (30) is formed on the arsenic diffusion layer (20). Thus, an insulating film (30) having an excellent insulating characteristic can be obtained, and therefore a MOS type semiconductor device with an excellent insulating characteristic can be obtained.

Abstract: A method for producing an impurity containing semiconductor substrate includes depositing an impurity on selected portions of the substrate by placing a charge on the substrate and converting a gaseous impurity containing atmosphere into a plasma. The impurity may then be diffused into the substrate to a controlled and shallow depth by employing a laser or the like to selectively irradiate the impurity.