Abstract: In a piezoelectric resonator, first and second resonance electrodes are provided on the upper surface and the lower surface of a piezoelectric member, inner electrode layers for leading the first and second resonance electrodes to the upper and lower surfaces are provided and extend to the upper and lower surfaces of the piezoelectric member, and connecting electrodes are provided on the upper and lower surfaces of the piezoelectric member, and are electrically connected to the corresponding resonance electrodes via the inner electrode layers.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circuit; forming the memory cells; exposing a surface of diffusion regions in the peripheral circuit after forming the memory cells; and forming a covering conductive layer on the exposed region of the diffusion regions in peripheral circuit. A semiconductor memory device produced by such a process has memory area having a good data retention due to a low junction leakage in the diffusion regions of the memory cells, whereas it has a high processing speed peripheral circuit due to a low resistance of the diffusion regions of the peripheral circuit.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: A surface mount type electronic component includes a substantially rectangular case substrate, an electronic element mounted on the case substrate along the longitudinal direction, and a cap which is fixed onto the case substrate in such a manner as to cover the electronic element. First and second top-surface electrodes and first and second bottom-surface electrodes, which extend along the width direction of the case substrate, are arranged with a spacing on the top surface and the bottom surface of the case substrate, respectively. The first top-surface electrode and the first bottom-surface electrode are connected to each other via a first side electrode disposed on the side surface of the case substrate, and the second top-surface electrode and the second bottom-surface electrode are connected to each other via a second side electrode disposed on the side surface of the case substrate.

Abstract: A surface mount type electronic component includes a substantially rectangular case substrate, an electronic element mounted on the case substrate along the longitudinal direction, and a cap which is fixed onto the case substrate in such a manner as to cover the electronic element. First and second top-surface electrodes and first and second bottom-surface electrodes, which extend along the width direction of the case substrate, are arranged with a spacing on the top surface and the bottom surface of the case substrate, respectively. The first top-surface electrode and the first bottom-surface electrode are connected to each other via a first side electrode disposed on the side surface of the case substrate, and the second top-surface electrode and the second bottom-surface electrode are connected to each other via a second side electrode disposed on the side surface of the case substrate.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: In a piezoelectric resonator, first and second resonance electrodes are provided on the upper surface and the lower surface of a piezoelectric member, inner electrode layers for leading the first and second resonance electrodes to the upper and lower surfaces are provided and extend to the upper and lower surfaces of the piezoelectric member, and connecting electrodes are provided on the upper and lower surfaces of the piezoelectric member, and are electrically connected to the corresponding resonance electrodes via the inner electrode layers.

Abstract: An energy-trapping piezoelectric vibration device generates a thickness shear mode and includes an elongated piezoelectric element having first and second longitudinally opposed ends, top and bottom surfaces provided between the first and second ends such that the top and bottom surfaces oppose each other, and beveled surfaces disposed at a vicinity of the first and second ends such that the thickness of the piezoelectric element gradually decreases towards the first and second ends, respectively. First and second vibration electrodes are disposed on the top surface and the bottom surface of the piezoelectric element, respectively. The first and second vibration electrodes are located at an approximate middle portion of the piezoelectric element so as to oppose each other with the piezoelectric element disposed therebetween, to define opposing portions which constitute a vibrator.

Abstract: A semiconductor device comprising a first connecting plug for bit contact and a second connecting plug for storage node contact buried in a first inter-layer insulating layer covering the transistor and projecting from the transistor. The bit line is buried in a second inter-layer insulating layer and connected to the first connecting plug. The electrode of the storage node is partially buried in the second inter-layer insulating layer, connected on the second connecting plug, and projected above the second inter-layer insulating layer.

Abstract: A semiconductor device wherein in formation of the wiring connection, an opening is made up to the middle of the insulating film, a side wall is formed, a burying wiring with the lower portion is arranged, a pad is formed, and a pad is formed in a polyplug contact without a masking step. Further, a conductive material is filled in the hole in the insulating film, a hole is opened in this material, a side wall is formed on the inner wall, a shrunken contact is opened by using this as a mask, and the conductive material is filled.

Abstract: A semiconductor device includes a transistor element having a gate electrode, a source•drain region and a channel region, a first interlayer insulator formed on the transistor element, a second interlayer insulator formed on the first interlayer insulator, an interconnecting line formed on the second interlayer insulator, a conductive material filling layer formed by burying a conductive material in a first hole which is formed in the first interlayer insulator on the source•drain region, and a contact plug formed in a second hole which is formed in the second interlayer insulator. This semiconductor device has a low sheet resistance, can perform high-speed operation and increase the degree of integration, has high reliability, and does not largely increase the number of fabrication steps. A method of fabricating the semiconductor device is also provided.

Abstract: A semiconductor device wherein in formation of the wiring connection, an opening is made up to the middle of the insulating film, a side wall is formed, a burying wiring with the lower portion is arranged, a pad is formed, and a pad is formed in a polyplug contact without a masking step. Further, a conductive material is filled in the hole in the insulating film, a hole is opened in this material, a side wall is formed on the inner wall, a shrunken contact is opened by using this as a mask, and the conductive material is filled.

Abstract: A capacitor-included, chip-type piezoelectric resonator allows minute and highly precise adjustment of electrostatic capacitance and the resonance frequency after production of the piezoelectric resonator by laminating a piezoelectric element and dielectric substrates. The resonator includes a piezoelectric substrate laminated with dielectric substrates and external electrodes disposed on the laminate body. A plurality of external electrodes are arranged to extend from the outer major surface of the first dielectric substrate to the outer major surface of the second dielectric substrate along first and second side surfaces disposed opposite to each other. On the outer major surface of the second dielectric substrate, at least one external electrode is divided into first and second electrode portions.

Abstract: An LDD-structured field-effect semiconductor device that can eliminate fluctuations in the threshold voltage caused by variations in the position of higher-density diffusion layers, thereby suppressing variations in the threshold voltage to a lower level. The junction depth of each of the lower-density diffusion layers in contact with a substrate is greater than the depth of a depletion layer at the place corresponding to a portion of the channel region contacting the source region. This prevents a change in the positional relationship between diffusion layers serving as, what are referred to as "pocket layers", and the depletion layer adjacent to the source, even though the position of the higher-density diffusion layers is varied in the longitudinal direction of the channel due to variations in the width of a spacer.

Abstract: An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+ -type diffusion layers and N-type diffusion layers and a resist for forming P.sup.+ -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be increased and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.

Abstract: When defective bits of a memory are remedied, the disclosed memory analyzing apparatus can execute remedy analysis of a large capacity memory freely and effectively in a short time. Data are transferred from a defect cell memory (3) provided for a memory tester body (1) to a remedy analyzing apparatus (2) in the sequence suitable for defect remedy. The transferred data are regenerated in address sequence, and the numbers of the defective bits are counted and stored in an X line defect memory (26) and a Y line defect memory (27) at the same time. Further, a line detect flag is raised on the basis of the number of detective bits in the same row and the same column. Further, with respect to the defective bits of a line other than the defect line, the addresses thereof are stored in the bit defect memory (35), and the number of the defect bits is stored in a unit region defect number memory (33) for each defect remedy unit region.

Abstract: Disclosed is a MOS transistor and a fabrication process for the MOS transistor. Each gate electrode pattern made of silicon is formed on a gate oxide film formed on a silicon base body. An impurity is doped in the silicon base body using the gate electrode patterns as a mask, followed by activation of the impurity thus doped, to form diffusion layers in a surface layer of the silicon base body. An interlayer insulating film is formed in such a manner as to cover the gate electrode patterns. An upper portion of the interlayer insulating film is removed to expose the upper portion of each gate electrode pattern. The gate electrode pattern thus exposed is removed by selective etching. After that, a recessed portion formed by removal of each gate electrode pattern is embedded with a metal material, to form a CMOS transistor.

Abstract: In a field effect semiconductor device, in order to increase the operation speed and to make the device finer by lowering the sheet resistance, and to lower the production cost by reducing the process steps, the diffusion layer 17 is surrounded by SiO.sub.2 films 16 and 34 covering the tungsten polycide layer 35 provided as the gate electrode and by the SiO.sub.2 film 12 in the device isolating region, and the titanium polycide layer 44 is brought into contact with the entire surface of the diffusion layer 17 while being extended on the SiO.sub.2 films 12 an d 16. Accordingly, a large allowance in aligning the contact hole 25 with respect to the titanium polycide layer 44 can be assured to make the contact compensation ion implantation unnecessary.