Patents by Inventor Hideaki Masuda
Hideaki Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240128282Abstract: A semiconductor device (10) according to one aspect of the present disclosure includes: a driving section (40) that drives an object to be driven; an abnormality detecting circuit (30), which is one example of an instruction circuit that outputs an instruction signal to the driving section (40); and a light amount detecting section (20) that detects an amount of incident light and invalidates the instruction signal output from the abnormality detecting circuit (30) in accordance with the amount of incident light.Type: ApplicationFiled: February 16, 2022Publication date: April 18, 2024Inventors: Koichi Okamoto, Hideaki Mogi, Takashi Masuda, Shinichirou Saeki, Mitsushi Tabata
-
Publication number: 20220162757Abstract: A plasma treatment device for forming a film on a substrate using plasma enhanced chemical vapor deposition includes an upper electrode and a substrate placing table on which the substrate is to be placed and which includes a heater configured to heat the substrate and a lower electrode opposed to the upper electrode. The device additionally includes a first side surface electrode that is embedded in a side surface of the substrate placing table and is spaced from the lower electrode. A second side surface electrode that is opposed to the first side surface electrode is disposed outside the substrate placing table.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Applicant: KIOXIA CORPORATIONInventor: Hideaki MASUDA
-
Patent number: 11098405Abstract: A shower head includes a face plate having an outer peripheral portion and a plurality of gas injection holes disposed inside the outer peripheral portion, a movable portion facing the face plate and having a gas introduction passage, and a seal interposed between the outer peripheral portion of the face plate and the movable portion. The movable portion is arranged to move, in the first direction, between a first position in which the movable portion is coupled to the face plate by interposing the seal between the movable portion and the face plate, and the gas introduction passage communicates with the inside of the chamber via the gas injection holes, and a second position in which the movable portion is separated from the face plate, and the gas introduction passage communicates with the inside of the chamber via a gap between the movable portion and the face plate.Type: GrantFiled: February 22, 2018Date of Patent: August 24, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hideaki Masuda, Nobuhide Yamada, Rikyu Ikariyama
-
Publication number: 20200080201Abstract: A plasma treatment device for forming a film on a substrate using plasma enhanced chemical vapor deposition includes an upper electrode and a substrate placing table on which the substrate is to be placed and which includes a heater configured to heat the substrate and a lower electrode opposed to the upper electrode. The device additionally includes a first side surface electrode that is embedded in a side surface of the substrate placing table and is spaced from the lower electrode. A second side surface electrode that is opposed to the first side surface electrode is disposed outside the substrate placing table.Type: ApplicationFiled: March 1, 2019Publication date: March 12, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Hideaki MASUDA
-
Publication number: 20190085453Abstract: A shower head includes a face plate having an outer peripheral portion and a plurality of gas injection holes disposed inside the outer peripheral portion, a movable portion facing the face plate and having a gas introduction passage, and a seal interposed between the outer peripheral portion of the face plate and the movable portion. The movable portion is arranged to move, in the first direction, between a first position in which the movable portion is coupled to the face plate by interposing the seal between the movable portion and the face plate, and the gas introduction passage communicates with the inside of the chamber via the gas injection holes, and a second position in which the movable portion is separated from the face plate, and the gas introduction passage communicates with the inside of the chamber via a gap between the movable portion and the face plate.Type: ApplicationFiled: February 22, 2018Publication date: March 21, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hideaki MASUDA, Nobuhide YAMADA, Rikyu IKARIYAMA
-
Patent number: 9953998Abstract: A method for manufacturing a semiconductor memory device includes forming a first insulating layer on a conductive layer; forming a second insulating layer on the first insulating layer, the second insulating layer including a first layer and a second layer having nitrogen and hydrogen bonds with higher density than a density thereof in the first layer; forming a third insulating layer on the second insulating layer; forming a semiconductor layer extending through the first insulating layer and the second insulating layer in a direction toward the third insulating layer from the conductive layer; selectively removing the second insulating layer to form a space, the first insulating layer being exposed in the space; forming the fourth insulating layer between the conductive layer and the first insulating layer, the fourth insulating layer being formed by thermally oxidizing the conductive layer through the first insulating layer in the space.Type: GrantFiled: September 7, 2016Date of Patent: April 24, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masahisa Sonoda, Hisataka Meguro, Hideaki Masuda
-
Patent number: 9953829Abstract: A semiconductor manufacturing method includes setting a relative position between first through holes of a first plate-shaped part and second through holes of a second plate-shaped part to a first relative position. The method includes supplying a first gas containing a component of the first film onto the semiconductor substrate in a reactor through the first through holes not closed with the second plate-shaped part, to form the first film on the semiconductor substrate. The method includes relatively moving the first plate-shaped part and the second plate-shaped part to change the relative position to a second relative position. The method includes supplying a second gas containing a component of the second film onto the semiconductor substrate through the first through holes not closed with the second plate-shaped part, to laminate the second film on the first film.Type: GrantFiled: January 21, 2016Date of Patent: April 24, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hideaki Masuda, Nobuhide Yamada
-
Publication number: 20180073143Abstract: According to one embodiment, the distance measuring device measures a distance in the first direction between the first plate electrode and the second plate electrode at three or more locations. The correcting device causes a plurality of sections of at least one of the first plate electrode or the second plate electrode to be movable in the first direction. The plurality of sections are separated from each other in a planar direction. The controller drives the correcting device based on a measurement result of the distance measuring device and moves at least one section of the plurality of sections of the at least one of the first plate electrode or the second plate electrode in the first direction.Type: ApplicationFiled: January 12, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Hideaki MASUDA
-
Patent number: 9780116Abstract: According to one embodiment, a semiconductor device includes a stacked body and a pillar. The stacked body includes insulating films, electrode films, and silicon containing films. Each of the insulating films and each of the electrode films are stacked alternately. One of the silicon containing films is provided between one of the insulating films and one of the electrode films. The pillar extends in the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a silicon pillar and a memory film. The silicon pillar extends in the stacking direction. The memory film is provided between the silicon pillar and one of the electrode films.Type: GrantFiled: December 8, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hideaki Masuda, Katsuyasu Shiba, Nobuhide Yamada
-
Publication number: 20170256562Abstract: A method for manufacturing a semiconductor memory device includes forming a first insulating layer on a conductive layer; forming a second insulating layer on the first insulating layer, the second insulating layer including a first layer and a second layer having nitrogen and hydrogen bonds with higher density than a density thereof in the first layer; forming a third insulating layer on the second insulating layer; forming a semiconductor layer extending through the first insulating layer and the second insulating layer in a direction toward the third insulating layer from the conductive layer; selectively removing the second insulating layer to form a space, the first insulating layer being exposed in the space; forming the fourth insulating layer between the conductive layer and the first insulating layer, the fourth insulating layer being formed by thermally oxidizing the conductive layer through the first insulating layer in the space.Type: ApplicationFiled: September 7, 2016Publication date: September 7, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Masahisa SONODA, Hisataka MEGURO, Hideaki MASUDA
-
Publication number: 20170104003Abstract: According to one embodiment, a semiconductor device includes a stacked body and a pillar. The stacked body includes insulating films, electrode films, and silicon containing films. Each of the insulating films and each of the electrode films are stacked alternately. One of the silicon containing films is provided between one of the insulating films and one of the electrode films. The pillar extends in the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a silicon pillar and a memory film. The silicon pillar extends in the stacking direction. The memory film is provided between the silicon pillar and one of the electrode films.Type: ApplicationFiled: December 8, 2016Publication date: April 13, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideaki MASUDA, Katsuyasu SHIBA, Nobuhide YAMADA
-
Publication number: 20170062202Abstract: A semiconductor manufacturing method includes setting a relative position between first through holes of a first plate-shaped part and second through holes of a second plate-shaped part to a first relative position. The method includes supplying a first gas containing a component of the first film onto the semiconductor substrate in a reactor through the first through holes not closed with the second plate-shaped part, to form the first film on the semiconductor substrate. The method includes relatively moving the first plate-shaped part and the second plate-shaped part to change the relative position to a second relative position. The method includes supplying a second gas containing a component of the second film onto the semiconductor substrate through the first through holes not closed with the second plate-shaped part, to laminate the second film on the first film.Type: ApplicationFiled: January 21, 2016Publication date: March 2, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hideaki MASUDA, Nobuhide YAMADA
-
Publication number: 20160268299Abstract: According to one embodiment, a semiconductor device includes a stacked body and a pillar. The stacked body includes insulating films, electrode films, and silicon containing films. Each of the insulating films and each of the electrode films are stacked alternately. One of the silicon containing films is provided between one of the insulating films and one of the electrode films. The pillar extends in the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a silicon pillar and a memory film. The silicon pillar extends in the stacking direction. The memory film is provided between the silicon pillar and one of the electrode films.Type: ApplicationFiled: September 10, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hideaki MASUDA, Katsuyasu SHIBA, Nobuhide YAMADA
-
Publication number: 20160237569Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a heater, a sidewall, and a moving mechanism. The heater is capable of heating a semiconductor substrate. The sidewall is located at an outer edge of the heater and protrudes upward from a mount face of the heater on which the semiconductor substrate is mounted. The moving mechanism relatively moves at least a part of the sidewall and the heater in a substantially perpendicular direction with respect to the mount face.Type: ApplicationFiled: September 8, 2015Publication date: August 18, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideaki MASUDA, Katsuyasu SHIBA
-
Patent number: 8993440Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.Type: GrantFiled: July 23, 2013Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
-
Publication number: 20140054754Abstract: Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized. Utilizing the material as a mask layer and subsequently removing the material enables a number of mask layers to be minimized in a subsequent filling operation (e.g., metallization). Material amenable to being in a first physical state and a second physical state is an optically reactive material. The optically reactive dielectric can comprise an element or compound which can act as an agent/catalyst in the optical conversion process along with any element or compound which can act as an accelerator for the optical reaction. Conversion can be brought about by exposure to electromagnetic radiation and/or application of thermal energy.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Tadayoshi Watanabe, Hideaki Masuda, Hideshi Miyajima
-
Publication number: 20130309866Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.Type: ApplicationFiled: July 23, 2013Publication date: November 21, 2013Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
-
Publication number: 20130171819Abstract: Described herein are methods for copper/low-k dielectric material integration. The methods involve depositing and curing a low-k dielectric material and depositing a mask on the low-k dielectric material. A via is patterned in the low-k dielectric material and a trench is patterned in the low-k dielectric material. After the via or trench is patterned, a portion of the low-k material is backfilled with a backfill material. The trench and via are filled with copper, then the mask and the copper filling the via are removed. After a first pre-CLN, the backfill material is removed. This creates a robust copper/porous low-k dielectric material interconnect.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Hideshi Miyajima, Hideaki Masuda
-
Publication number: 20100311240Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.Type: ApplicationFiled: March 17, 2010Publication date: December 9, 2010Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
-
Patent number: 7795142Abstract: A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.Type: GrantFiled: February 12, 2009Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Masuda, Hideshi Miyajima, Toshiaki Idaka