Patents by Inventor Hideaki Masuda

Hideaki Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090203201
    Abstract: A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.
    Type: Application
    Filed: February 12, 2009
    Publication date: August 13, 2009
    Inventors: Hideaki MASUDA, Hideshi MIYAJIMA, Toshiaki IDAKA
  • Patent number: 7569498
    Abstract: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film on the porous organo-siloxane film, and applying at least one of an electron beam and an ultraviolet ray to the porous organo-siloxane film and upper-side insulating film to cause polymerization reaction of the porogen component in the porous organo-siloxane film.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: August 4, 2009
    Assignees: Kabushiki Kaisha Toshiba, Sony Corporation
    Inventors: Hideaki Masuda, Hideshi Miyajima, Tsutomu Shimayama
  • Patent number: 7534717
    Abstract: The formation of an interlayer insulating film above a substrate, the formation of an insulating film of an organic material on the interlayer insulating film thereafter, and the irradiation of the insulating film of an organic material and the interlayer insulating film with electron beams, thereby curing at least the insulating film of an organic material, are proposed.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: May 19, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Keiji Fujita, Hideaki Masuda, Rempei Nakata, Miyoko Shimada
  • Publication number: 20080194117
    Abstract: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film on the porous organo-siloxane film, and applying at least one of an electron beam and an ultraviolet ray to the porous organo-siloxane film and upper-side insulating film to cause polymerization reaction of the porogen component in the porous organo-siloxane film.
    Type: Application
    Filed: January 25, 2008
    Publication date: August 14, 2008
    Inventors: Hideaki Masuda, Hideshi Miyajima, Tsutomu Shimayama
  • Patent number: 7154179
    Abstract: A semiconductor device, wherein an increase of a capacity between wiring layers is suppressed, reliability of wiring and property of withstand voltage of a diffusion prevention insulation film can be improved and the wiring resistance can be maintained low, is provided by comprising an interlayer insulation film formed on a substrate, a wiring formed on a trench pattern formed on the interlayer insulation film, and a diffusion prevention insulation film formed on an upper surfaces of the interlayer insulation film including the wiring and preventing diffusion of metal from the wiring; wherein the diffusion prevention insulation film has a middle layer between a lowermost layer and an uppermost layer, wherein the lowermost layer is formed so as to contact the upper surfaces of the interlayer insulation layer including the wiring, the uppermost layer constitutes an uppermost portion of the diffusion prevention insulation film, and the middle layer has a lower relative dielectric constant than those of the lower
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: December 26, 2006
    Assignees: Sony Corporation, Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Tabuchi, Hideshi Miyajima, Hideaki Masuda
  • Publication number: 20060199373
    Abstract: A manufacturing method of a semiconductor device, comprising providing a low-relative-dielectric-constant film above a substrate containing at least oxygen and having a relative dielectric constant of 3.3 or more, a conductor being to be buried in the film, performing a plasma processing by discharging a gas containing a noble gas as a main component to the film, the plasma processing being executed while the substrate above which the film is provided is storing in a processing chamber having an inside covered with a material composed of an element except for oxygen and substantially set under an oxygen-free atmosphere, and providing a first insulating film above the low-relative-dielectric-constant film by a plasma CVD method, being made of a material containing at least one of a material containing oxygen and a material containing an element reacting with oxygen, a conductor being to be buried in the first insulating film.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 7, 2006
    Inventors: Hideshi Miyajima, Hideaki Masuda, Tsutomu Shimayama, Shunichi Shibuki
  • Publication number: 20060017164
    Abstract: A semiconductor device, wherein an increase of a capacity between wiring layers is suppressed, reliability of wiring and property of withstand voltage of a diffusion prevention insulation film can be improved and the wiring resistance can be maintained low, is provided by comprising an interlayer insulation film formed on a substrate, a wiring formed on a trench pattern formed on the interlayer insulation film, and a diffusion prevention insulation film formed on an upper surfaces of the interlayer insulation film including the wiring and preventing diffusion of metal from the wiring; wherein the diffusion prevention insulation film has a middle layer between a lowermost layer and an uppermost layer, wherein the lowermost layer is formed so as to contact the upper surfaces of the interlayer insulation layer including the wiring, the uppermost layer constitutes an uppermost portion of the diffusion prevention insulation film, and the middle layer has a lower relative dielectric constant than those of the lower
    Type: Application
    Filed: May 16, 2005
    Publication date: January 26, 2006
    Inventors: Kiyotaka Tabuchi, Hideshi Miyajima, Hideaki Masuda
  • Publication number: 20050250311
    Abstract: The formation of an interlayer insulating film above a substrate, the formation of an insulating film of an organic material on the interlayer insulating film thereafter, and the irradiation of the insulating film of an organic material and the interlayer insulating film with electron beams, thereby curing at least the insulating film of an organic material, are proposed.
    Type: Application
    Filed: March 31, 2005
    Publication date: November 10, 2005
    Inventors: Hideshi Miyajima, Keiji Fujita, Hideaki Masuda, Rempei Nakata, Miyoko Shimada
  • Patent number: 6962870
    Abstract: A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench. The first non-porous film includes a first layer has a high etching selectivity ratio relative to the protective film, and a second layer has a high etching selectivity ratio relative to the resist mask and the second porous film.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: November 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Masuda, Hideshi Miyajima, Rempei Nakata
  • Publication number: 20040175930
    Abstract: A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench.
    Type: Application
    Filed: January 15, 2004
    Publication date: September 9, 2004
    Inventors: Hideaki Masuda, Hideshi Miyajima, Rempei Nakata