Abstract: Exemplary communication system 1 includes game devices 10, communication terminals 20, and game support server 30. Game devices 10 enable users to perform a multi-play activity. Each of communication terminals 20 runs an application associated with corresponding game device 10. Game support server 30 divides communication terminals 20 into separate communication groups in accordance with a situation of the multi-play activity performed by game devices 10 so that communication terminals 20 belonging to a same communication group can communicate with each other.

Abstract: A semiconductor device includes a semiconductor substrate, an internal circuit provided on the semiconductor substrate, a first and a second pads connected to the internal circuit, a first ESD protection circuit connectable to the first pad, and a second ESD protection circuit connectable to the second pad. The first ESD protection circuit includes a first ESD protection element, and the second ESD protection circuit includes a second and a third ESD protection elements. The second pad is connected to the internal circuit via the second ESD protection element, and the first pad is directly connected to the internal circuit.

Abstract: A test board includes a substrate, a socket mounted on the substrate and including a first connector pin to be connected to a first terminal of a semiconductor device when the semiconductor device is mounted in the socket, a plurality of external terminals through which a voltage or a signal is supplied to the first connector, first and second current paths that can be electrically connected between the first connector pin and one of the plurality of external terminals, and a connection mechanism. The first current path includes a first circuit element. The second current path includes no circuit element or a second circuit element that is different from the first circuit element. The connection mechanism is capable of electrically connecting the first connector pin to one of the plurality of external terminals via one of the first current path and the second current path.

Abstract: A semiconductor storage device includes first and second chips. The first chip has first bonding electrodes on a first surface. The second chip has second bonding electrodes on a second surface. The first surface is bonded to the second surface and the first bonding electrodes are electrically connected to the second bonding electrodes. One of the first and second chips has a first bonding pad electrode connectable to a bonding wire for data input/output. A first one of the first bonding electrodes is electrically connected to the first bonding pad electrode. The first chip has, on the first surface, a first insulating layer surrounding the first one of the first bonding electrodes and a second insulating layer that is farther from the first one of the first bonding electrodes than the first insulating layer and formed of a material different from that of the first insulating layer.

Abstract: A graphite crucible for silicon single crystal manufacturing by the Czochralski method, having a long life cycle, contains at least one gas venting hole provided in a corner portion of the crucible. Gas generated by reaction between the graphite crucible and a quartz crucible is released to the outside through the gas venting hole, and formation of SiC on the surface of the graphite crucible and deformation of the quartz crucible caused by the pressure of the generated gas are prevented.

Abstract: An ingot production method which makes it possible to greatly restrict formation of pinholes or substantially prevent them avoids the use of substantial amounts of small-sized polycrystalline silicon chunks of polycrystalline silicon chunks, only middle-sized polycrystalline silicon chunks and large-sized polycrystalline silicon chunks. In the step of filling polycrystalline silicon, the polycrystalline silicon chunks are randomly supplied into the crucible.

Abstract: According to the present invention, there is provided a method for designing a circuit, having, generating electrical filter graphic data indicating a candidate portion where a dimensional value of a layout pattern is permitted to deviate from a design value by taking account of an electrical characteristic, and electrical filter data indicating the permissible dimensional value in the candidate portion of the layout pattern by taking account of the electrical characteristic, by using circuit diagram data, a static timing analytical result, and a result of a circuit simulation, and store them in the storage unit, generating design data by using the electrical filter graphic data, and form a layout pattern by using the design data, detecting a lithography error by performing a lithography simulation on the layout pattern, determining by using the electrical filter database whether the error requires correction by taking account of the electrical characteristic, correcting the layout if the error is found to re

Abstract: Provided is a heat retention/cooling control device for a PM filter device, which controls the temperature of the outer periphery of the PM filter device to ensure an efficient burning in the PM filter device and prevents the influence of heat damage on the periphery of the PM filter device by effectively using moving air. An engine room and a cooling passage which are demarcated by a partition wall are provided in parallel in the front-back direction of an work machine, and an aftercooler, a cooling fan, and a PM filter device are provided in the cooling passage. When the exhaust temperature of exhaust gas is lower than a target temperature when PM is burned, the air volume of the cooling fan is controlled so as to decrease, thereby increasing the exhaust gas temperature. When the exhaust temperature of the exhaust gas is higher than the target temperature, the air volume of the cooling fan is controlled so as to increase, thereby enhancing the effect of cooling the outer periphery of the PM filter device.

Abstract: A graphite crucible for silicon single crystal manufacturing by the Czochralski method, having a long life cycle, contains at least one gas venting hole provided in a corner portion of the crucible. Gas generated by reaction between the graphite crucible and a quartz crucible is released to the outside through the gas venting hole, and formation of SiC on the surface of the graphite crucible and deformation of the quartz crucible caused by the pressure of the generated gas are prevented.

Abstract: In a semiconductor integrated circuit, a switching circuit controls the capacity of a capacitor unit based on a control signal from a control circuit and separates a resonant frequency determined by first inductance, second inductance, and the capacity of the capacitor unit from the band area of the signal handled by an A/D converter.

Abstract: An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.

Abstract: A layout design method includes extracting a plurality of pairs of complementary signals from signal lines connected between a plurality of circuit blocks, for every signal lines connected between the same circuit blocks, and routing the pairs by twisting each pair.

Abstract: An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.

Abstract: In a semiconductor integrated circuit, a switching circuit controls the capacity of a capacitor unit based on a control signal from a control circuit and separates a resonant frequency determined by first inductance, second inductance, and the capacity of the capacitor unit from the band area of the signal handled by an A/D converter.

Abstract: According to the present invention, there is provided a method for designing a circuit, having, generating electrical filter graphic data indicating a candidate portion where a dimensional value of a layout pattern is permitted to deviate from a design value by taking account of an electrical characteristic, and electrical filter data indicating the permissible dimensional value in the candidate portion of the layout pattern by taking account of the electrical characteristic, by using circuit diagram data, a static timing analytical result, and a result of a circuit simulation, and store them in the storage unit, generating design data by using the electrical filter graphic data, and form a layout pattern by using the design data, detecting a lithography error by performing a lithography simulation on the layout pattern, determining by using the electrical filter database whether the error requires correction by taking account of the electrical characteristic, correcting the layout if the error is found to re

Abstract: A level shift circuit for shifting levels of a pair of binary input signals having a first voltage range to produce a pair of binary output signals having a second voltage range includes a first circuit to shift a level of a first one of the binary input signals thereby to produce a first signal having the second voltage range, a second circuit to shift a level of a second one of the binary input signals thereby to produce a second signal having the second voltage range, and a timing adjustment circuit to produce the binary output signals by adjusting a pulse width thereof in response to the first and second signals such that the pulse width is equal to a time interval from when one of the first and second circuits stops level shift operation to when another one of the first and second circuits stops level shift operation.

Abstract: A reference voltage generating circuit is disclosed. The reference voltage generating circuit includes a collector layer where collectors of transistors are disposed, a base layer where bases of the transistors are disposed and which base layer is formed on the surface of the collector layer, and plural emitter layers in each of which an emitter of the transistor is disposed and which emitter layers are formed on the surface of the base layer that is common to the emitter layers.

Abstract: A level shift circuit for shifting levels of a pair of binary input signals having a first voltage range to produce a pair of binary output signals having a second voltage range includes a first circuit to shift a level of a first one of the binary input signals thereby to produce a first signal having the second voltage range, a second circuit to shift a level of a second one of the binary input signals thereby to produce a second signal having the second voltage range, and a timing adjustment circuit to produce the binary output signals by adjusting a pulse width thereof in response to the first and second signals such that the pulse width is equal to a time interval from when one of the first and second circuits stops level shift operation to when another one of the first and second circuits stops level shift operation.

Abstract: A system for analyzing a monolithic integrated circuit includes a logic circuit simulator configured to obtain a cell duty of a primitive cell configuring a logic circuit by performing a logic simulation of the logic circuit based on a netlist of the logic circuit and input vectors for the logic circuit, an analog circuit simulator configured to obtain a transistor duty of a transistor that configures a primitive cell by performing an analog simulation of the primitive cell based on a netlist of the analog circuit of the primitive cell and input vectors for the primitive cell, and a synthesis module configured to obtain a synthesized duty of a transistor of the logic circuit by performing a synthesis of the cell and transistor duties.

Abstract: First, circuit simulation programs are executed based on electric information of a schematic of a semiconductor integrated circuit. Then, LVS (layout versus schematic) programs are executed using the electric information of the schematic and physical layout information corresponding to the schematic. The semiconductor integrated circuit is therefore evaluated by processing circuit design value information obtained from the circuit simulation programs and layout information obtained by execution of the LVS programs.