Patents by Inventor Hideaki Numata

Hideaki Numata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120320667
    Abstract: A magnetic random access memory according to the present invention is provided with: a magnetic recording layer including a magnetization free region having a reversible magnetization, wherein a write current is flown through the magnetic recording layer in an in-plane direction; a magnetization fixed layer having a fixed magnetization; a non-magnetic layer provided between the magnetization free region and the magnetization fixed layer; and a heat sink structure provided to be opposed to the magnetic recording layer and having a function of receiving and radiating heat generated in the magnetic recording layer. The magnetic random access memory thus-structured radiates heat generated in the magnetic recording layer by using the heat sink structure, suppressing the temperature increase caused by the write current flown in the in-plane direction.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 20, 2012
    Applicant: NEC CORPORATION
    Inventors: Nobuyuki ISHIWATA, Hideaki NUMATA, Norikazu OHSHIMA
  • Publication number: 20120295406
    Abstract: A carbon nanotube dispersion liquid obtained by mixing carbon nanotubes, a first organic solvent that is a nonpolar solvent, and a second organic solvent that has a polarity higher than that of this first organic solvent and is compatible with this first organic solvent.
    Type: Application
    Filed: January 18, 2011
    Publication date: November 22, 2012
    Applicant: NEC CORPORATION
    Inventors: Hideaki Numata, Hiroyuki Endoh
  • Patent number: 8309992
    Abstract: A problem of a switching element using for the active layer a carbon nanotube (CNT) dispersion film that can be manufactured at low temperature has been that sufficient electrical contact and thermal conductivity between the CNTs and the source and drain electrode surfaces are not obtained. The switching element of the present invention has a structure in which a mixed layer of carbon nanotubes and a metal material, and a metal layer of the metal material are laminated in this order on source and drain electrodes, and thereby, the CNT-dispersed film and the electrode surfaces can be in firm electrical, mechanical, and thermal contact with each other. Thus, a switching element exhibiting good and stable transistor characteristics is obtained with a low-temperature, convenient, and low-cost process.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: November 13, 2012
    Assignee: NEC Corporation
    Inventors: Satoru Toguchi, Hideaki Numata, Hiroyuki Endoh
  • Patent number: 8253124
    Abstract: This invention provides a semiconductor element which uses a plurality of carbon nanotubes as a current path, can reduce contact resistance of its electrode contact part, and has excellent electrical characteristics. This semiconductor element is characterized in that the semiconductor element includes a current path (16) comprised of a plurality of carbon nanotubes (18) and not less than two electrodes (14, 15) connected with the current path, wherein at least one or more of the electrodes is made of a mixture of a metal and a carbon material (17) having SP2 hybridized orbital, such as a multi-walled carbon nanotube, a glassy carbon, and graphite particles.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: August 28, 2012
    Assignee: NEC Corporation
    Inventors: Hideaki Numata, Kazuki Ihara
  • Publication number: 20120206959
    Abstract: A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
    Type: Application
    Filed: March 29, 2012
    Publication date: August 16, 2012
    Inventors: TAKESHI HONDA, NOBORU SAKIMURA, TADAHIKO SUGIBAYASHI, HIDEAKI NUMATA, NORIKAZU OHSHIMA
  • Patent number: 8238135
    Abstract: A magnetic recording layer 10 of an MRAM has a first magnetization fixed region 11, a second magnetization fixed region 12 and a magnetization switching region 13. The magnetization switching region 13 has reversible magnetization and overlaps with a pinned layer. The first magnetization fixed region 11 is connected to a first boundary B1 of the magnetization switching region 13 and its magnetization direction is fixed to a first direction. The second magnetization fixed region 12 is connected to a second boundary B2 of the magnetization switching region 13 and its magnetization direction is fixed to a second direction. Both of the first direction and the second direction are toward the magnetization switching region 13 or away from the magnetization switching region 13. The damping coefficient ? in at least a portion R1, R2 of the magnetization fixed regions 11 and 12 is larger than the damping coefficient ? in the magnetization switching region 13.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: August 7, 2012
    Assignee: NEC Corporation
    Inventors: Tetsuhiro Suzuki, Norikazu Ohshima, Hideaki Numata
  • Publication number: 20110114914
    Abstract: An end portion (104a) of a first source electrode (104) and an end portion (105a) of a first drain electrode (105) face each other on a gate insulating film (103) via a channel formation region. The first source electrode (104) and first drain electrode (105) extend over steps, and the end portion (104a) and end portion (105a) face each other on the gate insulating film (103). The highest portions of the end portion (104a) and end portion (105a) are formed higher than the upper surface of the gate insulating film (103) serving as the channel formation region. A field-effect transistor of this invention also includes a second source electrode (107) which is formed in contact with the channel layer (106) and connects the first source electrode (104) and channel layer (106), and a second drain electrode (108) which is formed in contact with the channel layer (106) and connects, the first drain electrode (105) and channel layer (106).
    Type: Application
    Filed: June 19, 2009
    Publication date: May 19, 2011
    Inventors: Hideaki Numata, Satoru Toguchi, Hiroyuki Endoh
  • Patent number: 7929342
    Abstract: The present invention provides a new data writing method for an MRAM which can suppress deterioration of a tunnel barrier layer. A magnetic memory cell 1 has a magnetic recording layer 10 and a pinned layer 30 connected to the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 includes a magnetization switching region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization switching region 13 has reversible magnetization and faces the pinned layer 30. The first magnetization fixed region 11 is connected to a first boundary B1 of the magnetization switching region 13 and its magnetization direction is fixed to a first direction. The second magnetization fixed region 12 is connected to a second boundary B2 of the magnetization switching region 13 and its magnetization direction is fixed to a second direction.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: April 19, 2011
    Assignee: NEC Corporation
    Inventors: Hideaki Numata, Norikazu Ohshima, Tetsuhiro Suzuki, Tadahiko Sugibayashi, Nobuyuki Ishiwata, Shunsuke Fukami
  • Publication number: 20100252802
    Abstract: This invention provides a semiconductor element which uses a plurality of carbon nanotubes as a current path, can reduce contact resistance of its electrode contact part, and has excellent electrical characteristics. This semiconductor element is characterized in that the semiconductor element includes a current path (16) comprised of a plurality of carbon nanotubes (18) and not less than two electrodes (14, 15) connected with the current path, wherein at least one or more of the electrodes is made of a mixture of a metal and a carbon material (17) having SP2 hybridized orbital, such as a multi-walled carbon nanotube, a glassy carbon, and graphite particles.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 7, 2010
    Inventors: Hideaki Numata, Kazuki Ihara
  • Publication number: 20100224862
    Abstract: When an electronic element using a carbon nanotube (CNT) is fabricated, particularly when a carbon nanotube thin film is formed on a previously formed electrode, a CNT film is manufactured on the previously formed electrode, and the CNT film on the electrode is used as an electronic element, as it is. In this case, a problem is that unless the carbon nanotubes and the electrode are in sufficient contact with each other, the contact resistance increases, and sufficient element properties are not obtained. When a carbon nanotube thin film is formed on a previously formed electrode, a conductive organic polymer thin film is formed, before or after the carbon nanotube thin film is manufactured, to decrease the contact resistance.
    Type: Application
    Filed: September 2, 2008
    Publication date: September 9, 2010
    Inventors: Hiroyuki Endoh, Satoru Toguchi, Hideaki Numata
  • Publication number: 20100163858
    Abstract: A problem of a switching element using for the active layer a carbon nanotube (CNT) dispersion film that can be manufactured at low temperature has been that sufficient electrical contact and thermal conductivity between the CNTs and the source and drain electrode surfaces are not obtained. The switching element of the present invention has a structure in which a mixed layer of carbon nanotubes and a metal material, and a metal layer of the metal material are laminated in this order on source and drain electrodes, and thereby, the CNT-dispersed film and the electrode surfaces can be in firm electrical, mechanical, and thermal contact with each other. Thus, a switching element exhibiting good and stable transistor characteristics is obtained with a low-temperature, convenient, and low-cost process.
    Type: Application
    Filed: September 8, 2008
    Publication date: July 1, 2010
    Inventors: Satoru Toguchi, Hideaki Numata, Hiroyuki Endoh
  • Publication number: 20100149862
    Abstract: A magnetic random access memory comprises a magnetic recording layer equipped with a magnetization reversal region having a reversible magnetization and through which a write current is made to flow in the in-plane direction, a magnetization fixed layer having a fixed magnetization, a nonmagnetic layer provided between the magnetization reversal region and the magnetization fixed layer, and a heat absorbing structure provided opposing to the magnetic recording layer and having a function of receiving heat generated in the magnetic recording layer and of radiating the heat. Such magnetic random access memory can radiate heat generated in the magnetic recording layer by using the heat absorbing structure and prevent temperature rising caused by the write current flowing in the in-plane direction.
    Type: Application
    Filed: April 9, 2007
    Publication date: June 17, 2010
    Applicant: NEC CORPORATION
    Inventors: Nobuyuki Ishiwata, Hideaki Numata, Norikazu Ohshima
  • Publication number: 20100142264
    Abstract: The present invention provides a new data writing method for an MRAM which can suppress deterioration of a tunnel barrier layer. A magnetic memory cell 1 has a magnetic recording layer 10 and a pinned layer 30 connected to the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 includes a magnetization switching region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization switching region 13 has reversible magnetization and faces the pinned layer 30. The first magnetization fixed region 11 is connected to a first boundary B1 of the magnetization switching region 13 and its magnetization direction is fixed to a first direction. The second magnetization fixed region 12 is connected to a second boundary B2 of the magnetization switching region 13 and its magnetization direction is fixed to a second direction.
    Type: Application
    Filed: August 4, 2006
    Publication date: June 10, 2010
    Applicant: NEC CORPORATION
    Inventors: Hideaki Numata, Norikazu Ohshima, Tetsuhiro Suzuki, Tadahiko Sugibayashi, Nobuyuki Ishiwata, Shunsuke Fukami
  • Publication number: 20100096715
    Abstract: A magnetic recording layer 10 of an MRAM has a first magnetization fixed region 11, a second magnetization fixed region 12 and a magnetization switching region 13. The magnetization switching region 13 has reversible magnetization and overlaps with a pinned layer. The first magnetization fixed region 11 is connected to a first boundary B1 of the magnetization switching region 13 and its magnetization direction is fixed to a first direction. The second magnetization fixed region 12 is connected to a second boundary B2 of the magnetization switching region 13 and its magnetization direction is fixed to a second direction. Both of the first direction and the second direction are toward the magnetization switching region 13 or away from the magnetization switching region 13. The damping coefficient ? in at least a portion R1, R2 of the magnetization fixed regions 11 and 12 is larger than the damping coefficient ? in the magnetization switching region 13.
    Type: Application
    Filed: January 15, 2008
    Publication date: April 22, 2010
    Inventors: Tetsuhiro Suzuki, Norikazu Ohshima, Hideaki Numata
  • Publication number: 20090296454
    Abstract: A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
    Type: Application
    Filed: September 25, 2007
    Publication date: December 3, 2009
    Inventors: Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Hideaki Numata, Norikazu Ohshima
  • Patent number: 7177179
    Abstract: A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: February 13, 2007
    Assignee: NEC Corporation
    Inventors: Sadahiko Miura, Tadahiko Sugibayashi, Hideaki Numata, Kiyotaka Tsuji
  • Patent number: 7126201
    Abstract: A technique is provided in which an offset magnetic field of a memory cell of a MRAM is reduced more effectively. The MRAM of the present invention is composed of a free layer (11) which has a reversible free spontaneous magnetization, a fixed layer (6) which has fixed spontaneous magnetization, and a spacer layer (10) formed of non-magnetic interposed between the free layer (11) and the fixed layer (6). The fixed layer (6) is formed such that orange peel effect and magneto-static coupling effect does not substantially influence on the free layer (11).
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: October 24, 2006
    Assignee: NEC Corporation
    Inventors: Hisao Matsutera, Hideaki Numata
  • Publication number: 20060056250
    Abstract: A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.
    Type: Application
    Filed: April 21, 2003
    Publication date: March 16, 2006
    Applicant: NEC CORPORATION
    Inventors: Sadahiko Miura, Tadahiko Sugibayashi, Hideaki Numata, Kiyotaka Tsuji
  • Publication number: 20050242407
    Abstract: A technique is provided in which an offset magnetic field of a memory cell of a MRAM is reduced more effectively. The MRAM of the present invention is composed of a free layer (11) which has a reversible free spontaneous magnetization, a fixed layer (6) which has fixed spontaneous magnetization, and a spacer layer (10) formed of non-magnetic interposed between the free layer (11) and the fixed layer (6). The fixed layer (6) is formed such that orange peel effect and magneto-static coupling effect does not substantially influence on the free layer (11).
    Type: Application
    Filed: July 3, 2003
    Publication date: November 3, 2005
    Inventors: Hisao Matsutera, Hideaki Numata
  • Patent number: 6703249
    Abstract: A method of manufacturing a magnetic random access memory for excluding stress-induced defects in memory cells. The method is composed of forming a first magnetic film over a substrate, forming a tunnel insulating film on the first magnetic film such that the tunnel insulating film has a curvature, forming a second magnetic film on the tunnel insulating film, and etching the first magnetic film, the tunnel insulating film and the second magnetic film to form a memory cell. The etching is executed such that the curvature is excluded from the memory cell.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: March 9, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Takeshi Okazawa, Hideaki Numata