Abstract: A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.

Abstract: A technique is provided in which an offset magnetic field of a memory cell of a MRAM is reduced more effectively. The MRAM of the present invention is composed of a free layer (11) which has a reversible free spontaneous magnetization, a fixed layer (6) which has fixed spontaneous magnetization, and a spacer layer (10) formed of non-magnetic interposed between the free layer (11) and the fixed layer (6). The fixed layer (6) is formed such that orange peel effect and magneto-static coupling effect does not substantially influence on the free layer (11).

Abstract: A method of manufacturing a magnetic random access memory for excluding stress-induced defects in memory cells. The method is composed of forming a first magnetic film over a substrate, forming a tunnel insulating film on the first magnetic film such that the tunnel insulating film has a curvature, forming a second magnetic film on the tunnel insulating film, and etching the first magnetic film, the tunnel insulating film and the second magnetic film to form a memory cell. The etching is executed such that the curvature is excluded from the memory cell.

Abstract: A method of manufacturing a magnetic random access memory for excluding stress-induced defects in memory cells. The method is composed of forming a first magnetic film over a substrate, forming a tunnel insulating film on the first magnetic film such that the tunnel insulating film has a curvature, forming a second magnetic film on the tunnel insulating film, and etching the first magnetic film, the tunnel insulating film and the second magnetic film to form a memory cell. The etching is executed such that the curvature is excluded from the memory cell.

Abstract: A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell includes a magnetoresistance element and a switching element which establishes a resistive connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively correspond to the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and removing the voltage when the corresponding sense line is addressed, thereby discharging energy from the capacitive element through the resistive connection to the magnetoresistance element. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell.

Abstract: A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell has a magnetoresistance element and a switching element which establishes a connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively provided for the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and causing it to discharge when the corresponding sense line is addressed. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell. A number of voltage control elements are provided for maintaining the sense lines at constant lower voltages regardless of higher voltages produced by the sense circuits.

Abstract: A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell has a magnetoresistance element and a switching element which establishes a connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively provided for the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and causing it to discharge when the corresponding sense line is addressed. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell. A number of voltage control elements are provided for maintaining the sense lines at constant lower voltages regardless of higher voltages produced by the sense circuits.

Abstract: A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell includes a magnetoresistance element and a switching element which establishes a resistive connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively correspond to the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and removing the voltage when the corresponding sense line is addressed, thereby discharging energy from the capacitive element through the resistive connection to the magnetoresistance element. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell.

Abstract: In a magnetic random access memory circuit, the potential of all sense lines 121 to 124 are equalized, and the potential of all not-selected word lines 133, 135, 136 are equalized and the selected word line 134 is grounded so that a previously charged capacitor 114 is discharged by a current path passing from the capacitor 114 through a MOS transistor 118 maintaining the potential of the sense line 122 at a constant voltage lower than a break voltage, through the selected sense line 122, through the selected magneto-resistive element 142 and through the selected word line 134. Thus, a voltage applied to the magneto-resistive element is maintained at a level smaller than a voltage breaking the magneto-resistive elements or a voltage remarkably deteriorating the characteristics of the magneto-resistive elements because of a biasing effect when the tunnel magneto-resistive element is used, and on the other hand, a high precise and high speed reading can be realized.

Abstract: In a magnetic random access memory circuit, the potential of all sense lines 121 to 124 are equalized, and the potential of all not-selected word lines 133, 135, 136 are equalized and the selected word line 134 is grounded so that a previously charged capacitor 114 is discharged by a current path passing from the capacitor 114 through a MOS transistor 118 maintaining the potential of the sense line 122 at a constant voltage lower than a break voltage, through the selected sense line 122, through the selected magneto-resistive element 142 and through the selected word line 134. Thus, a voltage applied to the magneto-resistive element is maintained at a level smaller than a voltage breaking the magneto-resistive elements or a voltage remarkably deteriorating the characteristics of the magneto-resistive elements because of a biasing effect when the tunnel magneto-resistive element is used, and on the other hand, a high precise and high speed reading can be realized.

Abstract: A magnetic random access memory circuit comprises first and second row decoders receiving a part of a given address, first and second column decoders receiving the other part of a given address, a plurality of pairs of sense lines connected between output terminals of the first row decoder and output terminals of the second row decoder, each pair of sense lines being located adjacent to each other, a plurality of word lines connected between output terminals of the first column decoder and output terminals of the second column decoder, and extending to intersect the sense lines so that intersections of the sense lines and the word lines are located in the form of a matrix. A memory array includes a plurality of cell pairs distributed over the matrix, each cell pair including a memory cell and a reference cell located adjacent to each other. Each of the memory cell and the reference cell includes a magneto-resistive element.