Abstract: The present invention relates to a flame-retarded styrene-based plastic composition comprising (A) a styrene-based plastic material (B) a brominated aromatic compound having a melting point from 200° C. to 260° C. in which all bromine atoms are attached to the aromatic ring, (C) a brominated aromatic compound having a melting point above 300° C. in which all bromine atoms are attached to the aromatic ring, (D) an organic compound having at least one 2,3-dibromopropyl group, and optionally (E) antimony trioxide.

Abstract: A brominated polyphenylene oxide having a molecular skeleton obtained by condensing tribromophenols and satisfying the requirements: (A) its 20 wt. % solution in chloroform has an absorbance at 600 nm of not larger than 0.6; (B) when 50 ml of ion-exchanged water is added to its 1.00 g/30 ml solution in dioxane, the resulting solution has an electroconductivity of not larger than 10 &mgr;S/cm measured at 25° C.; and (C) when a mixture comprised of 20% by weight of the brominated polyphenylene oxide and 80% by weight of triphenyl phosphate is heated at 280° C. for 20 minutes, the halide ion increase therein is not larger than 10 &mgr;mols per gram of the brominated polyphenylene oxide, is used as a flame retardant. When it is added to resin, the resin moldings are excellent in its flame retardancy, electric properties, physical properties, thermal stability and appearance (color hue), and they do not corrode molds.

Abstract: A flame retarded polyolefin resin composition comprises polyolefin resin, 1 to 40 parts by weight per 100 parts of the polyolefin resin of a brominated bisphenol ether derivative of the formula: 1

Abstract: A flame retarded polyolefin resin composition comprises polyolefin resin, 1 to 40 parts by weight per 100 parts of the polyolefin resin of a brominated bisphenol ether derivative of the formula 1: 1

Abstract: A flame retarded polyamide or polyester resin composition is disclosed. The composition comprises (A) polyamide or polyester resin; (B) 3 to 50 parts by weight per 100 parts of said resin of brominated polystyrene or brominated polyphenylene ether; and (C) 10 to 10,000 ppm of said resin of a thermal coloration inhibitor selected from the group consisting of hydrazine, a hydrazino compound, a hydrazono compound and an acid addition salt thereof.

Abstract: The threshold voltages of transistors are set by controlling the amount of overlap in the direction of channel length between a channel region and a source region and the amount of overlap in the direction of channel length between the channel region and a drain region, whereby, in a semiconductor integrated circuit device in which transistors having different threshold voltages or different channel widths are mounted together, the ion injection conditions for the channel regions can be shared, thereby reducing the number of masks and the number of processing steps.

Abstract: A semiconductor thin film structure includes source/drain regions and a channel region positioned between the source/drain regions. The semiconductor thin film structure extends directly on and in contact with a surface of an insulation region. At least one of the source/drain regions includes a semiconductor material region extending directly over and in contact with the surface of the insulation region and a refractory metal silicide layer extending directly on and in contact with the semiconductor material region. The refractory metal silicide layer has a first thickness which is equal to or thicker than a half of a second thickness of the channel region, thereby suppressing any substantive kink effect.

Abstract: Disclosed is a method for fabricating semiconductor device, which has the steps of: forming a device separation region to section a first device forming region and a second device forming region on a substrate with a SOI structure; forming gate oxide film on the first and second device forming regions; introducing first conductivity type impurity and second conductivity type impurity into the first and second device forming regions to form a channel region of a first channel type transistor by the first conductivity type impurity and to form a source-drain region of the first channel type transistor by the second conductivity type impurity on at least the first device forming region; and introducing the first conductivity type impurity and the second conductivity type impurity selectively into the second device forming region to form a channel region and a source-drain region of a second channel type transistor on the second device forming region.

Abstract: A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating film is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.

Abstract: Disclosed is a method of manufacturing a semiconductor device having a reliable element isolation insulating film on an SOI substrate having an SOI layer. That is, the step of forming a semiconductor device on an SOI substrate includes the steps of sequentially depositing a silicon oxide film and an insulating film resistant to oxidation on the surface of the SOI layer of the SOI substrate to form a stacked film, etching the stacked film into a predetermined pattern shape to expose the SOI layer, selectively forming a thin silicon layer on the exposed SOI layer, and selectively thermally oxidizing the thin silicon layer and the exposed SOI layer by using the stacked film as a thermal oxidization mask. In the thermal oxidization step, all the thin silicon layer and the exposed SOI layer are thermally oxidized to be converted into an element isolation insulating film, and the element isolation insulating film is formed in contact with a buried oxide film below the region.

Abstract: The present invention provides a contact hole structure in a field effect transistor having a semiconductor layer extending over an insulation region, a control electrode provided on an insulation film on the semiconductor layer, and an inter-layer insulator covering the semiconductor layer and the control electrode. The semiconductor layer further comprises a drain region of a first conductivity type extending on the insulation region, an intermediate region of a second conductivity type extending on the insulation region and also being in contact with the drain region so that the intermediate region is positioned under the control electrode, and a laminated region in contact with the intermediate region so that the laminated region is separated by the intermediate region from the drain region. The laminated region comprises a base layer of the second conductivity type on the insulation region and a source region of the first conductivity type laminated on the base layer.

Abstract: A semiconductor integrated circuit device containing a protection MOSFET. This MOSFET has source and drain regions and a channel region formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The source region is made of a first lightly doped region and a first heavily doped region. The first lightly doped region is adjacent to a first end of the channel region. The drain region is made of a second lightly doped region and a second heavily doped region. The second lightly doped region is adjacent to a second end of the channel region. The second end of the channel region is positioned on an opposite side to that of the first end. A distance from the second end of the channel region to an opposing end of the second heavily doped region is longer than a distance from the first end of the channel region to an opposing end of the first heavily doped region.

Abstract: A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating firm is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.

Abstract: A valve timing control system for an internal combustion engine is provided. This system includes a sprocket assembly in driven connection with a crankshaft of the engine, a camshaft assembly disposing cams for opening and closing intake- and/or exhaust valves, and a ring gear assembly functioning as a piston slidably disposed between the sprocket assembly and the camshaft assembly for modifying a phase angle relation between the sprocket assembly and the camshaft assembly. The system further includes first and second pressure chambers for exerting fluid pressure on the ring gear assembly to be displaced over a range of first, second, and third positions which correspond to phase angle relations respectively suitable for low, intermediate, and high engine load levels.

Abstract: A valve timing control system for an internal combustion engine includes a hollow sprocket rotatably supported on a camshaft, and a rotary member housed within the sprocket and rigidly connected to the camshaft for rotation therewith. The rotary member has a pair of radially extending portions, on which a pair of gears are rotatably supported. The sprocket has an internal toothed circumference which is engageable with the gears to cause the gears to rotate in accordance with rotation of the sprocket for causing relative angular displacement of the rotary member to the sprocket. The valve timing control system further includes a pair of stopper pins for regulating relative angular displacement of the intermediate rotary member to the sprocket within a predetermined maximum range, and a clutch mechanism for restricting rotation of the gears.

Abstract: A valve timing control device for an internal combustion engine includes an intermediate rotary component disposed between an input component which is driven in synchronism with an engine revolution, and a cam drive component which is rigidly connected to a camshaft. The intermediate component is variable of positions relative to the input and cam drive components in order to adjust phase relationship between the input component and the cam drive component for setting valve timing at optimal timing relative to engine revolution cycle. The device includes a hydraulic means which selectively locks the intermediate component at a selected position where optimal phase relationship relative to the engine driving condition is established.