Patents by Inventor Hideaki Shishido

Hideaki Shishido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150214379
    Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 30, 2015
    Inventors: Shunpei YAMAZAKI, Takayuki ABE, Hideaki SHISHIDO
  • Publication number: 20150194446
    Abstract: To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a third period, a voltage based on a video signal voltage and the threshold voltage of the first transistor is held in the first and second storage capacitors; and in a fourth period, voltages held in the first and second storage capacitors are applied to a gate terminal of the first transistor to supply a current to a light-emitting element, so that the light-emitting element emits light. Through the operation process, a current obtained by compensating variations in the threshold voltage of the first transistor can be supplied to the light-emitting element, thereby variations in luminance can be suppressed.
    Type: Application
    Filed: March 18, 2015
    Publication date: July 9, 2015
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Shishido
  • Patent number: 9047809
    Abstract: To reduce a pseudo contour which occurs when displaying by a time gray scale method. When gradation is expressed with an n bit, bits each of which is shown by a binary of the gray scales are divided into three bit groups, and one frame is divided into two subframe groups. Then, a (0<a<n) subframes corresponding to bits belonging to a first bit group are divided into three or more, each about half of which is arranged in each subframe group; b (0<b<n) subframes corresponding to bits belonging to a second bit group are divided into two, each one of which is arranged in each the subframe group; and c (0?c<n and a+b+c=n) subframes corresponding to bits belonging to a third bit group are arranged in at least one of the subframe groups. And then, an overlapped time gray scale method is applied in each subframe group to express gradation.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Hideaki Shishido
  • Publication number: 20150144946
    Abstract: A display device that includes a capacitor with low power consumption even when the number of subpixels included in a pixel is increased is provided. The area of an opening in a subpixel that controls transmission of white light is smaller than the area of an opening in each of subpixels that control transmission of red light, green light, and blue light. A transistor included in each subpixel includes an oxide semiconductor film. The capacitor includes a first electrode and a second electrode. The first electrode is a metal oxide film in contact with an inorganic insulating film over the transistor. The second electrode is a light-transmitting conductive film that is over the inorganic insulating film and is electrically connected to the transistor.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventors: Koji KUSUNOKI, Hiroyuki MIYAKE, Hideaki SHISHIDO
  • Patent number: 9012918
    Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Abe, Hideaki Shishido
  • Patent number: 8988400
    Abstract: To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a third period, a voltage based on a video signal voltage and the threshold voltage of the first transistor is held in the first and second storage capacitors; and in a fourth period, voltages held in the first and second storage capacitors are applied to a gate terminal of the first transistor to supply a current to a light-emitting element, so that the light-emitting element emits light. Through the operation process, a current obtained by compensating variations in the threshold voltage of the first transistor can be supplied to the light-emitting element, thereby variations in luminance can be suppressed.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Shishido
  • Publication number: 20150060845
    Abstract: A semiconductor device includes a first and a second conductive films over an insulating surface; a first insulating film over the insulating surface and the first and the second conductive films; a semiconductor film overlapping with the first conductive film with the first insulating film provided therebetween; a third conductive film in contact with the semiconductor film; a fourth conductive film in contact with the semiconductor film and overlapping with the second conductive film with the first insulating film provided therebetween; a second insulating film including a thick region and a thin region, over the semiconductor film and the third and the fourth conductive films; a fifth conductive film overlapping with the semiconductor film with the second insulating film provided therebetween; and a sixth conductive film overlapping with the fourth conductive film over the thin region of the second insulating film.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventor: Hideaki SHISHIDO
  • Publication number: 20150053979
    Abstract: A semiconductor device including a plurality of pixels over a substrate and a display medium including an electronic ink over the substrate, in which at least one pixel of the plurality of pixels comprises first and second subpixels each of which comprises a transistor that comprises an oxide semiconductor including indium, and in which one image of at least one of the plurality of pixels is displayed by a plurality of signals, is provided.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventors: Hajime KIMURA, Hideaki SHISHIDO, Shunpei YAMAZAKI
  • Publication number: 20150042545
    Abstract: A pixel is divided into m (m is an integer of m?2) sub-pixels, and an area ratio of an s-th (s is an integer of 1 to m) sub-pixel is to be 2s-1. Also, k (k is an integer of k?2) sub-frame groups including a plurality of sub-frames are provided in one frame, along with dividing one frame into n (n is an integer of n?2) sub-frames, so that a ratio of a lighting period length of a t-th (t is an integer of 1 to n) sub-frame is 2(t-1)m. Further, each of the n sub-frames is divided into k sub-frames each having a lighting period length that is about 1/k of each of the n sub-frames, and one of these is provided in each of the k sub-frame groups.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventors: Hideaki Shishido, Hajime Kimura, Shunpei Yamazaki
  • Publication number: 20150034831
    Abstract: Provided is an imaging device that can correct an output value of a pixel circuit. The imaging device includes a pixel circuit, a current detection circuit, an A/D converter, one or more memory circuit portions, and an arithmetic circuit portion. The pixel circuit includes a transistor, a charge accumulation portion, and a light-receiving element. The memory circuit portion includes a first look-up table, a second look-up table, and a region where image data output from the arithmetic circuit portion is stored. The first look-up table stores data of potentials of the charge accumulation portion, which depends on the intensity of light. The second look-up table stores output data of the transistor, which depends on the potentials of the charge accumulation portion.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Hiroyuki MIYAKE, Hideaki SHISHIDO
  • Publication number: 20140374754
    Abstract: A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.
    Type: Application
    Filed: September 9, 2014
    Publication date: December 25, 2014
    Inventors: Atsushi Hirose, Hideaki Shishido
  • Patent number: 8913050
    Abstract: A plurality of transistors in which ratios of a channel length L to a channel width W, ?=W/L, are different from each other is provided in parallel as output side transistors 105a to 105c in a current mirror circuit 101 which amplifies a photocurrent of a photoelectric conversion device and an internal resistor is connected to each of the output side transistors 105a to 105c in series. The sum of currents which flow through the plurality of transistors and the internal resistor is output, whereby a transistor with large amount of ? can be driven in a linear range with low illuminance, and a transistor with small amount of ? can be driven in a linear range with high illuminance, so that applicable illuminance range of the photoelectric conversion device can be widened.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Atsushi Hirose
  • Publication number: 20140361959
    Abstract: In a display element such as an organic EL element, deterioration progresses due to light emission, and emission luminance is lowered even if the same voltage is applied to the display element. Therefore, use over time causes variations in luminance of each pixel, thereby a so-called “image burn-in” phenomenon occurs. Given this factor, the invention provides a display device which can reduce the difference in deterioration of a display element in each pixel and suppress variations in light emission of a display element in a pixel. It is prevented that only a specific pixel has a long accumulated lighting time. For that purpose, a gray scale of a display pattern is changed to prevent the difference in deterioration of display element in pixels from increasing. Alternatively, a specific display pattern is prevented from being fixedly displayed in a specific region.
    Type: Application
    Filed: May 9, 2014
    Publication date: December 11, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Atsushi UMEZAKI, Yasunori YOSHIDA, Hideaki SHISHIDO, Takuya KIMISHIMA, Yasuyuki ARAI
  • Publication number: 20140339553
    Abstract: To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Inventor: Hideaki SHISHIDO
  • Publication number: 20140306241
    Abstract: In a light-emitting device where reflective electrodes are regularly arranged, occurrence of interference fringes due to reflection of light reflected by the reflective electrode is inhibited. A surface of the reflective electrode of a light-emitting element is provided with a plurality of depressions. The shapes of the plurality of depressions are different from each other and do not have rotational symmetry. Irregularity of the surface shape of the reflective electrode is increased, which inhibits interference of light reflected by the reflective electrode. To form the plurality of depressions in the surface of the reflective electrode, for example, a surface of an insulating layer that is a base of the reflective electrode is made uneven. Reflecting the surface shape of the insulating layer, the reflective electrode has an uneven surface.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 16, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Mika Jikumaru, Yusuke Kubota, Daisuke Kubota, Tetsuji Ishitani, Hideaki Shishido
  • Patent number: 8860081
    Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner, wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Publication number: 20140301045
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 9, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Patent number: 8836034
    Abstract: A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Hirose, Hideaki Shishido
  • Publication number: 20140240631
    Abstract: Transistors each include a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A driver circuit portion includes first to third wirings formed in the same step as the gate electrode, fourth to sixth wirings formed in the same step as the source electrode and the drain electrode, a seventh wiring formed in the same step as a pixel electrode, a first region where the second wiring intersects with the fifth wiring, and a second region where the third wiring intersects with the sixth wiring. The first wiring is connected to the fourth wiring through the seventh wiring. A distance between the wirings in the second region is longer than that in the first region.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki SHISHIDO, Hiroyuki MIYAKE, Seiko INOUE, Kouhei TOYOTAKA, Koji KUSUNOKI
  • Patent number: 8796785
    Abstract: To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Shishido