Patents by Inventor Hideaki Tsuchiya
Hideaki Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923296Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.Type: GrantFiled: June 15, 2022Date of Patent: March 5, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naohito Suzumura, Kenichiro Sonoda, Hideaki Tsuchiya
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Publication number: 20230061976Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.Type: ApplicationFiled: June 15, 2022Publication date: March 2, 2023Inventors: Naohito SUZUMURA, Kenichiro SONODA, Hideaki TSUCHIYA
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Publication number: 20230067226Abstract: An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.Type: ApplicationFiled: June 23, 2022Publication date: March 2, 2023Inventors: Naohito SUZUMURA, Hiromichi TAKAOKA, Kenichiro SONODA, Hideaki TSUCHIYA, Yasutaka NAKASHIBA
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Patent number: 11335571Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.Type: GrantFiled: July 15, 2020Date of Patent: May 17, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hideaki Tsuchiya, Akira Matsumoto
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Publication number: 20220020604Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.Type: ApplicationFiled: July 15, 2020Publication date: January 20, 2022Inventors: Hideaki TSUCHIYA, Akira MATSUMOTO
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Patent number: 11063009Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.Type: GrantFiled: February 5, 2018Date of Patent: July 13, 2021Assignee: Renesas Electronics CorporationInventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
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Publication number: 20190237421Abstract: A semiconductor device includes a pad electrode formed over a semiconductor substrate, a conductor pillar formed on the pad electrode, a cap film formed on the conductor pillar and made of a nickel film, a terminal formed in a wiring board, a metal film formed on the terminal and made of a nickel film containing phosphorus, a solder layer interposed between the cap film and the metal film and containing tin as a main component, and an alloy layer interposed between the solder layer and the metal film and containing tin and copper.Type: ApplicationFiled: December 18, 2018Publication date: August 1, 2019Inventor: Hideaki TSUCHIYA
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Publication number: 20180294239Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.Type: ApplicationFiled: February 5, 2018Publication date: October 11, 2018Inventors: Kenji SAKATA, Toshihiko AKIBA, Takuo FUNAYA, Hideaki TSUCHIYA, Yuichi YOSHIDA
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Patent number: 10074740Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: GrantFiled: July 5, 2017Date of Patent: September 11, 2018Assignee: Renesas Electronics CorporationInventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20170301782Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: ApplicationFiled: July 5, 2017Publication date: October 19, 2017Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Patent number: 9722066Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: GrantFiled: February 28, 2016Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20170110399Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
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Patent number: 9559052Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.Type: GrantFiled: February 18, 2016Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
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Publication number: 20160181411Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: ApplicationFiled: February 28, 2016Publication date: June 23, 2016Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20160172298Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.Type: ApplicationFiled: February 18, 2016Publication date: June 16, 2016Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
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Patent number: 9293457Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: GrantFiled: July 15, 2015Date of Patent: March 22, 2016Assignee: Renesas Electronics CorporationInventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Patent number: 9281276Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.Type: GrantFiled: November 8, 2013Date of Patent: March 8, 2016Assignee: Renesas Electronics CorporationInventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
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Publication number: 20160020207Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: ApplicationFiled: July 15, 2015Publication date: January 21, 2016Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20150380382Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.Type: ApplicationFiled: September 10, 2015Publication date: December 31, 2015Inventors: Satoshi UNO, Hideaki TSUCHIYA, Shinji YOKOGAWA
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Patent number: 9159607Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.Type: GrantFiled: February 28, 2013Date of Patent: October 13, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Satoshi Uno, Hideaki Tsuchiya, Shinji Yokogawa