Patents by Inventor Hideaki Tsuchiya

Hideaki Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11343223
    Abstract: A communication apparatus connected to a virtual apparatus having an address dispensing function via an access network is provided, wherein the communication apparatus includes a communication confirmation unit configured to perform a communication confirmation between the virtual apparatus and the communication apparatus; and an address dispensing unit configured to dispense an address to a user terminal under control of the communication apparatus when communication between the virtual apparatus and the communication apparatus is not able to be confirmed by the communication confirmation unit, and the address dispensing unit causes the user terminal to forcibly release the address when the communication between the virtual apparatus and the communication apparatus is able to be confirmed by the communication confirmation unit.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 24, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Katsuma Miyamoto, Hideaki Iwata, Akihiro Okada, Hideo Tsuchiya, Shunsuke Homma, Akihiro Kimura
  • Patent number: 11335571
    Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: May 17, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Tsuchiya, Akira Matsumoto
  • Publication number: 20220020604
    Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 20, 2022
    Inventors: Hideaki TSUCHIYA, Akira MATSUMOTO
  • Patent number: 11063009
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
  • Publication number: 20190237421
    Abstract: A semiconductor device includes a pad electrode formed over a semiconductor substrate, a conductor pillar formed on the pad electrode, a cap film formed on the conductor pillar and made of a nickel film, a terminal formed in a wiring board, a metal film formed on the terminal and made of a nickel film containing phosphorus, a solder layer interposed between the cap film and the metal film and containing tin as a main component, and an alloy layer interposed between the solder layer and the metal film and containing tin and copper.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 1, 2019
    Inventor: Hideaki TSUCHIYA
  • Publication number: 20180294239
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Application
    Filed: February 5, 2018
    Publication date: October 11, 2018
    Inventors: Kenji SAKATA, Toshihiko AKIBA, Takuo FUNAYA, Hideaki TSUCHIYA, Yuichi YOSHIDA
  • Patent number: 10074740
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Publication number: 20170301782
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Application
    Filed: July 5, 2017
    Publication date: October 19, 2017
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Patent number: 9722066
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Grant
    Filed: February 28, 2016
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Publication number: 20170110399
    Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
  • Patent number: 9559052
    Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
  • Publication number: 20160181411
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Application
    Filed: February 28, 2016
    Publication date: June 23, 2016
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Publication number: 20160172298
    Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 16, 2016
    Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
  • Patent number: 9293457
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Patent number: 9281276
    Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: March 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
  • Publication number: 20160020207
    Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).
    Type: Application
    Filed: July 15, 2015
    Publication date: January 21, 2016
    Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
  • Publication number: 20150380382
    Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Inventors: Satoshi UNO, Hideaki TSUCHIYA, Shinji YOKOGAWA
  • Patent number: 9159607
    Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 13, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Uno, Hideaki Tsuchiya, Shinji Yokogawa
  • Publication number: 20150228586
    Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.
    Type: Application
    Filed: November 8, 2013
    Publication date: August 13, 2015
    Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
  • Patent number: 8749058
    Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hideaki Tsuchiya, Yukio Miura, Tomoyuki Nakamura, Koichi Ohto, Chikako Ohto, Shinji Yokogawa