Patents by Inventor Hideaki Uchida

Hideaki Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10601411
    Abstract: A comparator includes a differential pair circuit comprising NMOS transistors, the differential pair circuit configured to output a signal corresponding to a difference between first and second input signals supplied thereto, and an input circuit configured to raise a voltage level of the first input signal supplied to the differential pair circuit when the voltage of the first input signal is less than a predetermined threshold value.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: March 24, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiichi Goya, Hideaki Uchida, Norihiro Ueda
  • Publication number: 20180226960
    Abstract: A comparator includes a differential pair circuit comprising NMOS transistors, the differential pair circuit configured to output a signal corresponding to a difference between first and second input signals supplied thereto, and an input circuit configured to raise a voltage level of the first input signal supplied to the differential pair circuit when the voltage of the first input signal is less than a predetermined threshold value.
    Type: Application
    Filed: September 3, 2017
    Publication date: August 9, 2018
    Inventors: Seiichi GOYA, Hideaki UCHIDA, Norihiro UEDA
  • Patent number: 8465933
    Abstract: Lactobacillus screening methods were carried out using surface plasmon resonance spectrums and human intestinal mucin and blood group antigens as probes. A trial to set selection criteria in the above-mentioned methods of screening for lactobacilli was made to adapt the methods to mass screening, and it was discovered that lactobacilli compatible with ABO blood groups can be screened by setting 100 RU as a criterion for judging bacterial binding under certain conditions. Using 238 lactobacillus strains, the above-mentioned screening methods and tests to judge their compatibility for the use of yogurt production were carried out, to at long last specifically discover bacillus strains compatible with blood groups A, B, and O.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: June 18, 2013
    Assignee: Meiji Co., Ltd
    Inventors: Tadao Saito, Yasushi Kawai, Hideaki Uchida, Katsunori Kimura, Kakuhei Isawa, Keisuke Furuichi
  • Publication number: 20110104721
    Abstract: Lactobacillus screening methods were carried out using surface plasmon resonance spectrums and human intestinal mucin and blood group antigens as probes. A trial to set selection criteria in the above-mentioned methods of screening for lactobacilli was made to adapt the methods to mass screening, and it was discovered that lactobacilli compatible with ABO blood groups can be screened by setting 100 RU as a criterion for judging bacterial binding under certain conditions. Using 238 lactobacillus strains, the above-mentioned screening methods and tests to judge their compatibility for the use of yogurt production were carried out, to at long last specifically discover bacillus strains compatible with blood groups A, B, and O.
    Type: Application
    Filed: January 10, 2011
    Publication date: May 5, 2011
    Inventors: Tadao Saito, Yasushi Kawai, Hideaki Uchida, Katsunori Kimura, Kakuhei Isawa, Keisuke Furuichi
  • Patent number: 7897374
    Abstract: Lactobacillus screening methods were carried out using surface plasmon resonance spectrums and human intestinal mucin and blood group antigens as probes. A trial to set selection criteria in the above-mentioned methods of screening for lactobacilli was made to adapt the methods to mass screening, and it was discovered that lactobacilli compatible with ABO blood groups can be screened by setting 100 RU as a criterion for judging bacterial binding under certain conditions. Using 238 lactobacillus strains, the above-mentioned screening methods and tests to judge their compatibility for the use of yogurt production were carried out, to at long last specifically discover bacillus strains compatible with blood groups A, B, and O.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: March 1, 2011
    Assignee: Meiji Dairires Corporation
    Inventors: Tadao Saito, Yasushi Kawai, Hideaki Uchida, Katsunori Kimura, Kakuhei Isawa, Keisuke Furuichi
  • Publication number: 20100247500
    Abstract: The survival of lactic acid bacterial strains such as probiotic bacteria contained in yogurt etc. is improved. A lactic acid bacterium survival improver including a propionic acid bacterium fermentation product to improve the survival of a lactic acid bacterium. The propionic acid bacterium is a bacterium belonging to the genus Propionibacterium. The bacterium belonging to the genus Propionibacterium is Propionibacterium freudenreichii.
    Type: Application
    Filed: November 18, 2008
    Publication date: September 30, 2010
    Inventors: Kakuhei Isawa, Hideaki Uchida, Keisuke Furuichi, Fuyuko Yamamoto
  • Publication number: 20080160565
    Abstract: Lactobacillus screening methods were carried out using surface plasmon resonance spectrums and human intestinal mucin and blood group antigens as probes. A trial to set selection criteria in the above-mentioned methods of screening for lactobacilli was made to adapt the methods to mass screening, and it was discovered that lactobacilli compatible with ABO blood groups can be screened by setting 100 RU as a criterion for judging bacterial binding under certain conditions. Using 238 lactobacillus strains, the above-mentioned screening methods and tests to judge their compatibility for the use of yogurt production were carried out, to at long last specifically discover bacillus strains compatible with blood groups A, B, and O.
    Type: Application
    Filed: December 1, 2005
    Publication date: July 3, 2008
    Applicant: MEIJI DAIRIES CORPORATION
    Inventors: Tadao Saito, Yasushi Kawai, Hideaki Uchida, Katsunori Kimura, Kakuhei Isawa, Keisuke Furuichi
  • Publication number: 20070137525
    Abstract: A water-soluble inorganic composition obtained by reacting an inorganic dissolution promoter with at least one solute selected from the group consisting of metal silicon, boric acid, and borax at a ratio of the inorganic dissolution promoter to the solute of 1:10 to 1:100 by weight, wherein the inorganic dissolution promoter is obtained by mixing in water (A) at least one compound selected from the group consisting of an alkali metal fluoride, an alkali metal phosphite, an alkali metal sulfite, an Alkali metal nitrite, sulfurous acid, nitrous acid, and phosphorous acid, alkali metal phosphate, alkali metal nitrate, alkali metal sulfate, phosphoric acid, nitric acid, sulfuric acid and (B) at least one alkali metal hydroxide at a ratio of (A):(B) of 1:9 to 4:1 by weight; a plasticized substance; and a foamed inorganic substance are provided.
    Type: Application
    Filed: January 4, 2007
    Publication date: June 21, 2007
    Applicant: HIROSHI KOKUTA
    Inventors: Hiroshi Kokuta, Katsuhiro Kokuta, Hideaki Uchida, Kenji Kokuta, Naoto Kokuta
  • Publication number: 20050075410
    Abstract: The invention provides an inorganic dissolution accelerator used for obtaining a water-soluble inorganic compound(s), high in concentration and containing a large solid content, which accelerator is prepared by making one or more compounds selected from fluorides, mineral acids, mineral “ous” acids and salts thereof, and boric acid compounds, all either natural or synthetic, coexist with an alkali metal and/or substance containing an alkaline metal, and is able to transform metals and inorganic substances present in water, either natural or synthetic, containing as the main component silicon Si, aluminum Al, and/or boron B, into amorphous highly water-soluble inorganic compounds having the solubilities equal to, or larger than those well known in the art.
    Type: Application
    Filed: February 8, 2002
    Publication date: April 7, 2005
    Inventors: Hiroshi Kokuta, Katsuhiro Kokuta, Hideaki Uchida, Kenji Kokuta, Naoto Kokuta
  • Patent number: 6864559
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Publication number: 20040231563
    Abstract: An aqueous film forming inorganic composition which is prepared by reacting metallic silicon and an alkali metal hydroxide in an aqueous solvent in the presence of at least one compound selected from the group consisting of a fluoride and sulfurous acid, nitrous acid, phosphorous acid and a salt of the acid, characterized in that it has a pH value of 10 to 13 at 20° C. and comprises colloidal particles of the product of the above reaction having various, that is, relatively large, medium and relatively small particle diameters; an inorganic foam prepared by heating the composition to 150° C. or higher; and methods for preparing the composition and the foam. The aqueous film forming inorganic composition can be suitably used for preparing an inorganic foam and a thermally insulating composite material which are excellent in thermal insulation, and is not pollutant to the environment and can be recycled in the environment.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 25, 2004
    Inventors: Hiroshi Kokuta, Katsuhiro Kokuta, Hideaki Uchida, Kenji Kokuta, Naoto Kokuta
  • Patent number: 6740958
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: May 25, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Publication number: 20030178699
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 25, 2003
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Publication number: 20020153591
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 24, 2002
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6208010
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: March 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6166726
    Abstract: A power supply applies a power-supply voltage VDD to operate an LCD driver circuit. A booster circuit increases the power-supply voltage VDD, generating an LCD-driving voltage VLDC. When the power-supply voltage VDD is equal to or higher than a predetermined voltage, a power-supply voltage detecting circuit outputs the LCD-driving voltage VLCD to a switch circuit. The switch circuit disconnects the line for applying the voltage VLCD, from the line for applying a reference voltage GND. When the power-supply voltage VDD is lower than the predetermined voltage, the power-supply voltage detecting circuit outputs an indefinite voltage to the switch circuit. In this case, the switch circuit short-circuits the line for applying the voltage VLCD, to the line for applying the reference voltage GND. This prevents undesired phenomena, such as flickering, from occurring on the screen of the liquid crystal display, even if the application of power-supply voltage VDD is interrupted.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Uchida, Kouji Ohhashi
  • Patent number: 5680066
    Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitu
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: October 21, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira Ide, Masahiro Yamamura, Hideaki Uchida
  • Patent number: 5637434
    Abstract: In a method for producing a toner for electrostatic development, a mixture of starting toner materials comprising at least a resin and a colorant is kneaded, extruded and cooled to obtain a toner material. The toner material is crushed and then pulverized by an impact pulverizer having a pulverizing section formed by disposing a stator having ridges of a triangular waveform at an inner surface thereof and a rotor having ridges of a triangular waveform at an outer surface thereof at a gap between the ridges of the stator and of the rotor.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 10, 1997
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Susumi Ikushima, Shingo Ishiyama, Sadaki Yagi, Hideaki Uchida
  • Patent number: 5619151
    Abstract: A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; a
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira ide, Masahiro Yamamura, Hideaki Uchida
  • Patent number: 5513091
    Abstract: A voltage transforming circuit comprises a constant-voltage regulator circuit for receiving a first voltage from a first voltage source and outputting a second voltage having the same polarity as the first voltage and a predetermined absolute value lower than the same, a step-up circuit, having a plurality of output terminals, for receiving the second voltage and a first synchronization signal, the step-up circuit stepping up the absolute value of the second voltage and controlling the operation of charging capacitors, thereby outputting from the output terminals a plurality of stepped-up voltages of the same polarity having absolute values higher than the second voltage, a level shifter circuit for receiving a second synchronization signal which uses the first voltage as one of logic levels, and receiving that one of the stepped-up voltages which has a highest absolute value higher than that of the first voltage, the level shifter circuit shifting the voltage of the one of logic levels to the highest absolut
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: April 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Uchida, Kouji Oohashi