Patents by Inventor Hideaki Yamakoshi

Hideaki Yamakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230068923
    Abstract: The present technology relates to an imaging device, an imaging method, and an electronic device enabling to improve image quality. Two or more imaging units capable of imaging or sensing a same subject are included, in which at least one first imaging unit among the two or more imaging units includes a first filter configured to transmit a plurality of wavelength bands, and at least another one second imaging unit other than the first imaging unit among the two or more imaging units includes a second filter capable of varying a wavelength band. The present technology can be applied to, for example, a compound-eye camera module, an imaging device including a compound-eye camera module, a device that includes an imaging device and provides virtual reality or the like.
    Type: Application
    Filed: February 12, 2021
    Publication date: March 2, 2023
    Inventors: Hideaki Yamakoshi, Masashi Nakata
  • Patent number: 11217599
    Abstract: A plurality of select transistors are formed in a first region of a semiconductor substrate, a plurality of memory transistors are formed in a second region of the semiconductor substrate, and a drain region of the select transistor and a source region of the memory transistor are electrically connected to form a memory cell. Here, the first region and the second region are arranged with each other in a gate width direction of the select transistor and the memory transistor.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideaki Yamakoshi
  • Patent number: 11145744
    Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichiro Abe, Takashi Hashimoto, Hideaki Yamakoshi, Yuto Omizu
  • Patent number: 11049869
    Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 29, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Shinichiro Abe, Takashi Hashimoto, Yuto Omizu
  • Patent number: 10777569
    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuto Omizu, Takashi Hashimoto, Hideaki Yamakoshi
  • Publication number: 20200243545
    Abstract: A plurality of select transistors are formed in a first region of a semiconductor substrate, a plurality of memory transistors are formed in a second region of the semiconductor substrate, and a drain region of the select transistor and a source region of the memory transistor are electrically connected to form a memory cell. Here, the first region and the second region are arranged with each other in a gate width direction of the select transistor and the memory transistor.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 30, 2020
    Inventor: Hideaki YAMAKOSHI
  • Patent number: 10651188
    Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Publication number: 20190363095
    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 28, 2019
    Inventors: Yuto OMIZU, Takashi HASHIMOTO, Hideaki YAMAKOSHI
  • Patent number: 10483273
    Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Publication number: 20190348429
    Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Hideaki YAMAKOSHI, Takashi HASHIMOTO, Shinichiro ABE, Yuto OMIZU
  • Publication number: 20190279998
    Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 12, 2019
    Inventors: Hideaki YAMAKOSHI, Shinichiro ABE, Takashi HASHIMOTO, Yuto OMIZU
  • Patent number: 10325899
    Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keiichi Maekawa, Hideaki Yamakoshi, Shinichiro Abe, Hideki Makiyama, Tetsuya Yoshida, Yuto Omizu
  • Publication number: 20180366556
    Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.
    Type: Application
    Filed: April 19, 2018
    Publication date: December 20, 2018
    Inventors: Shinichiro ABE, Takashi Hashimoto, Hideaki Yamakoshi, Yuto Omizu
  • Publication number: 20180301463
    Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 18, 2018
    Inventors: Hideaki YAMAKOSHI, Takashi HASHIMOTO, Shinichiro ABE, Yuto OMIZU
  • Publication number: 20180286881
    Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.
    Type: Application
    Filed: January 15, 2018
    Publication date: October 4, 2018
    Inventors: Hideaki YAMAKOSHI, Takashi HASHIMOTO, Shinichiro ABE, Yuto OMIZU
  • Publication number: 20180286850
    Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.
    Type: Application
    Filed: January 25, 2018
    Publication date: October 4, 2018
    Inventors: Keiichi Maekawa, Hideaki Yamakoshi, Shinichiro Abe, Hideki Makiyama, Tetsuya Yoshida, Yuto Omizu
  • Patent number: 10050040
    Abstract: A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM cell that holds information at a storage node, a nonvolatile memory cell, and a transistor. The nonvolatile memory cell holds information by use of the first threshold voltage as an erase state and the second threshold voltage as a write state, and shifts to the write state by a write voltage being applied in the erase state. The transistor selects whether or not to apply the write voltage (voltage of a write voltage line) to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 14, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideaki Yamakoshi
  • Patent number: 10026744
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: July 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Publication number: 20180090501
    Abstract: A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM cell that holds information at a storage node, a nonvolatile memory cell, and a transistor. The nonvolatile memory cell holds information by use of the first threshold voltage as an erase state and the second threshold voltage as a write state, and shifts to the write state by a write voltage being applied in the erase state. The transistor selects whether or riot to apply the write voltage (voltage of a write voltage line) to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 29, 2018
    Inventor: Hideaki YAMAKOSHI
  • Publication number: 20180047742
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 15, 2018
    Inventors: Hideaki YAMAKOSHI, Takashi HASHIMOTO, Shinichiro ABE, Yuto OMIZU