Patents by Inventor Hideaki Yamakoshi
Hideaki Yamakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180040365Abstract: A semiconductor device which suppresses soft errors and functions as a non-volatile memory and a method for manufacturing the same. In the semiconductor device, a first non-volatile memory element and a second non-volatile memory element are electrically coupled to a first memory node and a second memory node through a first MOS transistor and a second MOS transistor respectively. A first capacitor and a second capacitor each have a storage node electrically coupled to the first memory node and the second memory node respectively and each have a cell plate to form a capacitance between the storage node and the cell plate.Type: ApplicationFiled: June 23, 2017Publication date: February 8, 2018Applicant: Renesas Electronics CorporationInventors: Yukio MAKI, Yoshiyuki ISHIGAKI, Toshiaki TAI, Hideaki YAMAKOSHI, Toshihiko HIROSE, Takuya ISHIDA
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Patent number: 9508554Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.Type: GrantFiled: September 29, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Kazuharu Yamabe, Shinichiro Abe, Shoji Yoshida, Hideaki Yamakoshi, Toshio Kudo, Seiji Muranaka, Fukuo Owada, Daisuke Okada
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Patent number: 9472289Abstract: In order to reduce a chip area of a semiconductor device having a non-volatile memory, a configuration is adopted, in which a length in a second direction of a capacity electrode of an element for writing/erasing data is made smaller than both a length in the second direction of a gate electrode of an element for reading data formed by part of the same floating electrode and a length in the second direction of a capacity electrode of a capacitive element. Herein, by recessing, of the side surfaces of the capacity electrode of the element for writing/erasing data, the side surface on the side opposite to the capacity electrode of the other element for writing/erasing data adjacent to the former element for writing/erasing data, a length in the second direction of an active region where the element for writing/erasing data is arranged is reduced.Type: GrantFiled: January 20, 2016Date of Patent: October 18, 2016Assignee: Renesas Electronics CorporationInventor: Hideaki Yamakoshi
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Publication number: 20160232977Abstract: In order to reduce a chip area of a semiconductor device having a non-volatile memory, a configuration is adopted, in which a length in a second direction of a capacity electrode of an element for writing/erasing data is made smaller than both a length in the second direction of a gate electrode of an element for reading data formed by part of the same floating electrode and a length in the second direction of a capacity electrode of a capacitive element. Herein, by recessing, of the side surfaces of the capacity electrode of the element for writing/erasing data, the side surface on the side opposite to the capacity electrode of the other element for writing/erasing data adjacent to the former element for writing/erasing data, a length in the second direction of an active region where the element for writing/erasing data is arranged is reduced.Type: ApplicationFiled: January 20, 2016Publication date: August 11, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventor: HIDEAKI YAMAKOSHI
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Publication number: 20160093499Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.Type: ApplicationFiled: September 29, 2015Publication date: March 31, 2016Inventors: Kazuharu YAMABE, Shinichiro ABE, Shoji YOSHIDA, Hideaki YAMAKOSHI, Toshio KUDO, Seiji MURANAKA, Fukuo OWADA, Daisuke OKADA
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Publication number: 20160071858Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.Type: ApplicationFiled: November 16, 2015Publication date: March 10, 2016Inventors: Hideaki Yamakoshi, Daisuke Okada
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Patent number: 9196363Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.Type: GrantFiled: December 29, 2014Date of Patent: November 24, 2015Assignee: Renesas Electronics CorporationInventors: Hideaki Yamakoshi, Daisuke Okada
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Publication number: 20150187782Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.Type: ApplicationFiled: December 29, 2014Publication date: July 2, 2015Inventors: Hideaki Yamakoshi, Daisuke Okada
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Patent number: 8994092Abstract: A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, ?7 V is applied to the drain of a selected nonvolatile memory cell, ?8 V is applied to the gate electrode of the selection transistor, and further ?3 V is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed. Thereby, a selected nonvolatile memory cell is discriminated from an unselected nonvolatile memory cell.Type: GrantFiled: December 11, 2013Date of Patent: March 31, 2015Assignee: Renesas Electronics CorporationInventor: Hideaki Yamakoshi
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Publication number: 20140167132Abstract: A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, ?7 V is applied to the drain of a selected nonvolatile memory cell, ?8 V is applied to the gate electrode of the selection transistor, and further ?3 V is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed. Thereby, a selected nonvolatile memory cell is discriminated from an unselected nonvolatile memory cell.Type: ApplicationFiled: December 11, 2013Publication date: June 19, 2014Applicant: Renesas Electronics CorporationInventor: Hideaki Yamakoshi
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Publication number: 20140140133Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.Type: ApplicationFiled: January 27, 2014Publication date: May 22, 2014Applicant: Renesas Electronics CorporationInventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
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Patent number: 8304820Abstract: Processing of memory cells forming a nonvolatile memory in a semiconductor device. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.Type: GrantFiled: November 24, 2011Date of Patent: November 6, 2012Assignee: Renesas Electronics CorporationInventors: Hideaki Yamakoshi, Hideyuki Yashima, Shinichiro Abe, Yasuhiro Taniguchi
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Publication number: 20120061745Abstract: There is provided a technology capable of improving the processing precision of memory cells forming a nonvolatile memory in a semiconductor device including the nonvolatile memory. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.Type: ApplicationFiled: November 24, 2011Publication date: March 15, 2012Inventors: HIDEAKI YAMAKOSHI, HIDEYUKI YASHIMA, SHINICHIRO ABE, YASUHIRO TANIGUCHI
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Patent number: 8076191Abstract: In processing memory cells for forming a nonvolatile memory in a semiconductor device, a second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.Type: GrantFiled: April 1, 2010Date of Patent: December 13, 2011Assignee: Renesas Electronics CorporationInventors: Hideaki Yamakoshi, Hideyuki Yashima, Shinichiro Abe, Yasuhiro Taniguchi
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Publication number: 20110233639Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.Type: ApplicationFiled: March 13, 2011Publication date: September 29, 2011Inventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
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Publication number: 20100255647Abstract: There is provided a technology capable of improving the processing precision of memory cells forming a nonvolatile memory in a semiconductor device including the nonvolatile memory. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.Type: ApplicationFiled: April 1, 2010Publication date: October 7, 2010Inventors: Hideaki YAMAKOSHI, Hideyuki Yashima, Shinichiro Abe, Yasuhiro Taniguchi