Patents by Inventor Hidefumi Mukai
Hidefumi Mukai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8975178Abstract: According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.Type: GrantFiled: September 4, 2012Date of Patent: March 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Keisuke Kikutani, Satoshi Nagashima, Hidefumi Mukai, Takehiro Kondoh, Hisataka Meguro
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Patent number: 8728888Abstract: In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array. A second mandrel is formed on the hard-mask material in a region of a selection gate transistor. First sidewall-masks are formed on side-surfaces of the first mandrels. A second sidewall-mask is formed on a side-surface of the second mandrel. An upper side-surface of the second sidewall-mask is exposed. A sacrificial film is embedded between the first sidewall-masks. A sacrificial spacer is formed on the upper side-surface of the second sidewall-mask. A resist film covers the second mandrel. An outer edge of the resist film is located between the first mandrel closest to the second mandrel and the sacrificial spacer. The first mandrels are removed using the resist film as a mask. And, the sacrificial film and spacer are removed.Type: GrantFiled: March 12, 2013Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Iida, Satoshi Nagashima, Nagisa Takami, Hidefumi Mukai, Yoshihiro Yanai
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Publication number: 20140065812Abstract: In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array. A second mandrel is formed on the hard-mask material in a region of a selection gate transistor. First sidewall-masks are formed on side-surfaces of the first mandrels. A second sidewall-mask is formed on a side-surface of the second mandrel. An upper side-surface of the second sidewall-mask is exposed. A sacrificial film is embedded between the first sidewall-masks. A sacrificial spacer is formed on the upper side-surface of the second sidewall-mask. A resist film covers the second mandrel. An outer edge of the resist film is located between the first mandrel closest to the second mandrel and the sacrificial spacer. The first mandrels are removed using the resist film as a mask. And, the sacrificial film and spacer are removed.Type: ApplicationFiled: March 12, 2013Publication date: March 6, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Naoyuki IIDA, Satoshi Nagashima, Nagisa Takami, Hidefumi Mukai, Yoshihiro Yanai
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Publication number: 20130237051Abstract: According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.Type: ApplicationFiled: September 4, 2012Publication date: September 12, 2013Inventors: Keisuke KIKUTANI, Satoshi NAGASHIMA, Hidefumi MUKAI, Takehiro KONDOH, Hisataka MEGURO
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Patent number: 8440376Abstract: According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.Type: GrantFiled: January 14, 2011Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Kazuya Fukuhara, Michiya Takimoto, Hidefumi Mukai, Soichi Inoue
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Patent number: 8423926Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.Type: GrantFiled: September 20, 2011Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Koshiba, Hidefumi Mukai, Seiro Miyoshi, Kazunori Iida
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Publication number: 20120174045Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.Type: ApplicationFiled: September 20, 2011Publication date: July 5, 2012Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Seiro Miyoshi, Kazunori IIda
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Patent number: 8196071Abstract: A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.Type: GrantFiled: January 15, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiromitsu Mashita, Katsumi Iyanagi, Takafumi Taguchi, Toshiya Kotani, Hidefumi Mukai, Taiga Uno, Takashi Nakazawa
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Patent number: 8178366Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.Type: GrantFiled: January 27, 2011Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Seiro Miyoshi, Hidefumi Mukai, Takeshi Koshiba
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Publication number: 20120020158Abstract: A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).Type: ApplicationFiled: July 20, 2011Publication date: January 26, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tohru OZAKI, Mitsuhiro Noguchi, Hideaki Maekawa, Hiromitsu Mashita, Takafumi Taguchi, Kazuhito Kobayashi, Hidefumi Mukai, Hiroyuki Nitta
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Publication number: 20110300646Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.Type: ApplicationFiled: January 27, 2011Publication date: December 8, 2011Inventors: Seiro MIYOSHI, Hidefumi MUKAI, Takeshi KOSHIBA
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Publication number: 20110177458Abstract: According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.Type: ApplicationFiled: January 14, 2011Publication date: July 21, 2011Inventors: Toshiya KOTANI, Kazuya Fukuhara, Michiya Takimoto, Hidefumi Mukai, Soichi Inoue
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Publication number: 20110143271Abstract: A pattern generating method includes obtaining an on-substrate pattern by performing a process for forming the on-substrate pattern by simulation or experiment based on a design pattern of the on-substrate pattern formed by an imprint process using a template, employing the design pattern when a comparison result of the design pattern and obtained on-substrate pattern satisfies a predetermined condition, and correcting the design pattern to satisfy the predetermined condition when the comparison result does not satisfy the predetermined condition.Type: ApplicationFiled: June 24, 2010Publication date: June 16, 2011Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Kazuhito Kobayashi, Takumi Ota
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Patent number: 7941782Abstract: In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.Type: GrantFiled: November 21, 2007Date of Patent: May 10, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Kai, Kazuo Hatakeyama, Hidefumi Mukai, Hiromitsu Mashita, Koji Hashimoto
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Patent number: 7941767Abstract: A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.Type: GrantFiled: April 30, 2008Date of Patent: May 10, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hidefumi Mukai, Shinji Yamaguchi, Yukiyasu Arisawa, Toshiya Kotani
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Publication number: 20110012297Abstract: A pattern transfer method for transferring an uneven pattern onto a resist material is disclosed. The uneven pattern is formed in a template having a through-groove in a predetermined region. The resist material is applied to a substrate. The template is made to come into contact with the resist material. The resist material is filled to concave portion in the uneven pattern. The residual resist material leaked from a gap between the substrate and the template to the outside is sucked through the through-groove in a state where the template is in contact with the resist material. The resist material is made to cure in a state where the template is in contact with the resist material after the suction of the residual resist material. The template is separated from the cured resist material.Type: ApplicationFiled: March 5, 2010Publication date: January 20, 2011Inventors: Ayumi KOBIKI, Takeshi Koshiba, Hidefumi Mukai, Seiro Miyoshi
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Patent number: 7851914Abstract: A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag along the first direction, and coupling portions of the upper contact and the lower contact are displaced from the center of the upper contact in a second direction perpendicular to the first direction.Type: GrantFiled: March 19, 2009Date of Patent: December 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Masukawa, Koji Hashimoto, Hidefumi Mukai, Kosuke Yanagidaira
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Publication number: 20100266960Abstract: A method of manufacturing a semiconductor device according to an embodiment includes determining a second exposure parameter including exposure parameters except for an exposure amount from a dimension distribution information so that a resist pattern of a first resist pattern formed based on a second pattern has a desired dimension in a plurality of regions to be shot within a surface of a wafer.Type: ApplicationFiled: March 10, 2010Publication date: October 21, 2010Inventors: Hiromitsu MASHITA, Toshiya KOTANI, Michiya TAKIMOTO, Hidefumi MUKAI, Takafumi TAGUCHI, Kazuya FUKUHARA
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Publication number: 20100202181Abstract: A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.Type: ApplicationFiled: September 17, 2009Publication date: August 12, 2010Inventors: Takaki HASHIMOTO, Hidefumi Mukai, Yasunobu Kai, Toshiya Kotani
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Publication number: 20100187714Abstract: A pattern generation method of generating a three-dimensional pattern to be formed at a template for use in a method of forming a pattern by filling a resist material in the three-dimensional pattern of the template includes performing at least one of adjustment of a depth of the three-dimensional pattern and division of the three-dimensional pattern, based on a relationship between a filling time of the resist material and a dimension or shape of the three-dimensional pattern.Type: ApplicationFiled: January 22, 2010Publication date: July 29, 2010Inventors: Ayumi KOBIKI, Takeshi KOSHIBA, Hidefumi MUKAI, Yasutada NAKAGAWA, Seiro MIYOSHI