Patents by Inventor Hidehiko Iwasaki
Hidehiko Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010049800Abstract: RAID information and physical position information of hard disk units are managed by a disk controller in a mapped fashion. When the physical position of the hard disk units is changed, the information mapping is retried. Further, the positional information of the hard disk units accommodated in a disk array system under the administration of the disk controller, is calculated so as to form n-dimensional coordinate system information, and the resulting information is stored in each of the hard disk units. When the hard disk units are inserted into the disk array system, the n-dimensional coordinate system information is read from each hard disk unit. If it is detected that there is difference from the current coordinate system information, then information before removal and that after the insertion are compared with each other and a data link is reconstructed.Type: ApplicationFiled: February 20, 2001Publication date: December 6, 2001Inventors: Katsuyoshi Suzuki, Kenichi Takamoto, Kenji Muraoka, Hidehiko Iwasaki
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Patent number: 6321346Abstract: In an external storage, an I/O process is continued without any intervention of a user or a host system at failure of a controller. When a failure occurs in a controller, a host system 10 recognizes the failure of the controller. Before the failure is notified to the user and application to stop the job, the substitutive controller reads the SCSI-ID possessed by an SCSI port of the failed controller from a shared memory, registers the SCSI-ID of the SCSI port to the SCSI port associated with the substitutive controller, and erases by a port address resetting facility 45 of the substitutive controller the SCSI-ID possessed by an SCSI port of the failed controller. Thanks to the provision, since the SCSI-ID specified at issuance of an I/O request is transferred between the controllers, the user or the host system need not alter the I/O request issuing route. Moreover, while the host system does not recognize the error, the transfer can be conducted.Type: GrantFiled: October 20, 1999Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Akira Murotani, Toshio Nakano, Hidehiko Iwasaki, Kenji Muraoka
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Publication number: 20010020282Abstract: In an external storage, an I/O process is continued without any intervention of a user or a host system at failure of a controller. When a failure occurs in a controller, a host system 10 recognizes the failure of the controller. Before the failure is notified to the user and application to stop the job, the substitutive controller reads the SCSI-ID possessed by an SCSI port of the failed controller from a shared memory, registers the SCSI-ID of the SCSI port to the SCSI port associated with the substitutive controller, and erases by a port address resetting facility 45 of the substitutive controller the SCSI-ID possessed by an SCSI port of the failed controller. Thanks to the provision, since the SCSI-ID specified at issuance of an I/O request is transferred between the controllers, the user or the host system need not alter the I/O request issuing route. Moreover, while the host system does not recognize the error, the transfer can be conducted.Type: ApplicationFiled: April 17, 2001Publication date: September 6, 2001Inventors: Akira Murotani, Toshio Nakano, Hidehiko Iwasaki, Kenji Muraoka
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Publication number: 20010011333Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.Type: ApplicationFiled: March 13, 2001Publication date: August 2, 2001Inventors: Akemi Sanada, Toshio Nakano, Hidehiko Iwasaki, Masahiko Sato, Kenji Muraoka, Kenichi Takamoto, Masaaki Kobayashi
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Publication number: 20010011332Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.Type: ApplicationFiled: March 13, 2001Publication date: August 2, 2001Inventors: Akemi Sanada, Toshio Nakano, Hidehiko Iwasaki, Masahiko Sato, Kenji Muraoka, Kenichi Takamoto, Masaaki Kobayashi
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Publication number: 20010009024Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.Type: ApplicationFiled: March 13, 2001Publication date: July 19, 2001Inventors: Akemi Sanada, Toshio Nakano, Hidehiko Iwasaki, Masahiko Sato, Kenji Muraoka, Kenichi Takamoto, Masaaki Kobayashi
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Publication number: 20010008010Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.Type: ApplicationFiled: March 13, 2001Publication date: July 12, 2001Inventors: Akemi Sanada, Toshio Nakano, Hidehiko Iwasaki, Masahiko Sato, Kenji Muraoka, Kenichi Takamoto, Masaaki Kobayashi
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Patent number: 6057974Abstract: A method and system which prevents starting-up problems in plural magnetic disk storage devices included in a disk array system during restart following halt of the magnetic disk storage devices after long term operation. The disk array system includes the plural magnetic disk storage devices, a microprocessor unit (MPU) which controls the magnetic disk storage devices, a control memory, a parity calculator, and cache memory. The control memory contains a operation time control table in which a tolerable continuous operation time Ti and a halt time Ts are stored. Each of the magnetic disk storage devices is intentionally stopped individually for the halt time Ts at time interval of the tolerable continuous operation time Ti.Type: GrantFiled: July 18, 1997Date of Patent: May 2, 2000Assignee: Hitachi, Ltd.Inventors: Tsutomu Sukigara, Hidehiko Iwasaki, Takashi Takenaka, Mitsuhiko Oguchi, Yuichi Otani
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Patent number: 6052795Abstract: In an external storage, an I/O process continues without any intervention of a user of a host system upon failure of a controller. When a failure occurs in a controller, a host system recognizes the failure of the controller. Before the failure is notified to the user and application program to stop the job, the substitute controller reads the SCSI-ID possessed by an SCSI port of the failed controller from a shared memory, registers the SCSI-ID of the SCSI port to the SCSI port associated with the substitute controller, and erases by a port address resetting facility of the substitute controller the SCSI-ID possessed by an SCSI port of the failed controller. Due to such provision, since the SCSI-ID specified at issuance of an I/O request is transferred between the controllers, the user or the host system need not alter the I/O request issuing route.Type: GrantFiled: October 29, 1996Date of Patent: April 18, 2000Assignee: Hitachi, Ltd.Inventors: Akira Murotani, Toshio Nakano, Hidehiko Iwasaki, Kenji Muraoka
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Patent number: 6012119Abstract: A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation.Type: GrantFiled: January 26, 1998Date of Patent: January 4, 2000Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 5819054Abstract: A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation.Type: GrantFiled: March 17, 1997Date of Patent: October 6, 1998Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 5530830Abstract: A disk array system having a plurality of disk units includes an upper-level data transfer controller for controlling transfer of data to and from an upper-level apparatus, a data buffer for temporarily storing therein data from the upper-level apparatus, a drive data transfer controller for controlling the data transfer between the buffer and the units, and a main microprocessor for controlling the the transfer controllers. When transferring data, the microprocessor indicates an address to be used in the buffer and a distribution mode of data to the data transfer controllers so that the data transfer is conducted thereafter without intervention of the microprocessor. During the transfer, the microprocessor can generate information for a subsequent data transfer to indicate the information to the transfer controllers. After a data transfer is terminated, the pertinent transfer controller can immediately execute the next data transfer, which increases the utilization efficiency of the data bus.Type: GrantFiled: December 6, 1993Date of Patent: June 25, 1996Assignees: Hitachi, Ltd., Hitachi Computer Peripherals Co., Ltd.Inventors: Hidehiko Iwasaki, Ryoichi Suzuki, Yoshinori Tsuneda, Katsutoshi Mizuno, Hidemi Baba