Patents by Inventor Hidehiko Suzuki

Hidehiko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030129454
    Abstract: A magnetoresistive sensor including a first antiferromagnetic layer, a pinned ferromagnetic layer provided on the first antiferromagnetic layer, a first nonmagnetic conductive layer provided on the pinned ferromagnetic layer, a free ferromagnetic layer provided on the first nonmagnetic conductive layer, and a second nonmagnetic conductive layer provided on the free ferromagnetic layer. The magnetoresistive sensor further includes a specular layer provided on the second nonmagnetic conductive layer, and an interlayer coupling control layer provided on the specular layer. The interlayer coupling control layer is provided by a second antiferromagnetic layer or a hard ferromagnetic layer.
    Type: Application
    Filed: December 18, 2002
    Publication date: July 10, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Hidehiko Suzuki
  • Patent number: 6560219
    Abstract: A hybrid exchange which exchanges the STM data to be transmitted periodically to realize an exchange in unit of the ATM data to be transmitted asynchronously includes asynchronous transmission terminal interface as the interface with an STM terminal, an synchronous transmission terminal interface as the interface with an ATM terminal, an ATM exchange interface as the interface with an ATM exchange, a transmitting unit for transmitting the STM time slot and ATM time slot, and a control unit for controlling the interfaces. The synchronous transmission terminal interface assigns the STM data to be transmitted periodically to the STM time slot, while the asynchronous transmission terminal interface assigns the ATM data to be transmitted asynchronously to the ATM time slot. The STM time slot and ATM time slot are identified by the STM/ATM identifier. The STM time slot is stored by multiplexing a plurality of STM data.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: May 6, 2003
    Assignee: Fujitsu Limited
    Inventors: Takashi Tabu, Masami Murayama, Sachiko Inoue, Hidehiko Suzuki, Yoshihiro Kubota, Kohei Ueki
  • Publication number: 20020196393
    Abstract: An object of the present invention is to provide a liquid crystal display, which can surely perform an instillation process used when liquid crystal is sealed between substrates in a cell process, and a fabrication method thereof. A liquid crystal display comprises a sealing material 6 made of a photo-curing type material which seals liquid crystal 22 sandwiched between substrates 4 and 16, and a shading film 8 having a shading area which overlays a red-colored layer 28 transmitting red light, a green-colored layer 26 transmitting green light and a blue-colored layer 24 transmitting blue light, wherein only the blue-colored layer 24 is formed in an area of the shading film contacting with the sealing material 6 and the photo-curing type material of the sealing material is structured to have a light reactive area for a wavelength of blue color band.
    Type: Application
    Filed: May 20, 2002
    Publication date: December 26, 2002
    Applicant: Fujitsu Limited
    Inventors: Kunihiro Tashiro, Takuya Yoshimi, Yoshio Koike, Satoru Imai, Hideaki Tsuda, Hiroyasu Inoue, Satoshi Murata, Hidehiko Suzuki, Hidefumi Yoshida, Tadashi Hasegawa, Yoji Taniguchi, Norimichi Nakayama, Hiroyuki Sugimura, Minoru Otani
  • Publication number: 20020109948
    Abstract: A magnetic head of a magnetoresistance type is provided. The magnetic head comprises a magnetoresistance film, an underlying layer formed on each of both sides of the magnetoresistance film, and a magnetic-domain regulating film formed on the underlying layer so as to regulate a magnetic domain of a free magnetic layer in the magnetoresistance film. The underlying layer has a laminated structure of a tungsten-(W)-group metal layer formed on a tantalum-(Ta)-group metal layer. The underlying layer is formed so thick as to arrange the magnetic-domain regulating film at a position corresponding to the free magnetic layer.
    Type: Application
    Filed: September 24, 2001
    Publication date: August 15, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Kenichiro Yamada, Naoki Mukoyama, Hidehiko Suzuki, Hitoshi Kanai
  • Publication number: 20020074975
    Abstract: A switching DC-to-DC converter having at least one power channel including an inductor and a controller which generates at least one power switch control signal for at least one power switch of each power channel. The converter is configured to operate in a continuous mode when the inductor current remains above zero, to enter a discontinuous pulse skipping mode of operation when the inductor current falls to zero (which occurs when the load current is below a threshold value), and to leave the discontinuous pulse skipping mode and resume continuous mode operation when the inductor current rises above zero.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 20, 2002
    Inventors: Barry James Culpepper, Hidehiko Suzuki
  • Patent number: 6396252
    Abstract: A switching DC-to-DC converter having at least one power channel including an inductor and a controller which generates at least one power switch control signal for at least one power switch of each power channel. The converter is configured to operate in a continuous mode when the inductor current remains above zero, to enter a discontinuous pulse skipping mode of operation when the inductor current falls to zero (which occurs when the load current is below a threshold value), and to leave the discontinuous pulse skipping mode and resume continuous mode operation when the inductor current rises above zero.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: May 28, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Barry James Culpepper, Hidehiko Suzuki
  • Patent number: 6285174
    Abstract: An on-time signal generation circuit for use in a switching DC-to-DC converter, a switching DC-to-DC converter including such a circuit, and a method for generating an on-time signal which is a binary pulse train comprising pulses TON, where the width of each pulse TON is equal to TOSC (Vout/Vin), where TOSC, Vin, and Vout are, respectively, the switching period and the input potential of a DC-to-DC converter, and a control potential. The control potential Vout is one of the output potential of the DC-to-DC converter and a DC potential proportional to a desired level of such output potential. The on-time signal generation circuit includes a comparator, a ramp generator with an output coupled to one input of the comparator, and an amplifier with an output coupled to the other input of the comparator. The ramp generator generates a periodic ramped potential having peak level kVin and period Tosc.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: September 4, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Hidehiko Suzuki
  • Patent number: 4847549
    Abstract: A switching voltage regulator is stabilized against changes in input voltage by suppressing the increase in loop gain due to increased input voltage. The reduction of loop gain is achieved by use of a modified triangle waveform which is compared to an error signal to switch the regulator output stage.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: July 11, 1989
    Assignee: National Semiconductor Corporation
    Inventor: Hidehiko Suzuki