Abstract: It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase in a design period by circuit tuning. A local block control circuit comprises an end detecting section for receiving a plurality of complete signals, a transfer control section for generating a stop signal having a negative logic to determine whether or not a system clock is supplied to a processing block upon receipt of an end signal output from the end detecting section, the system clock and a handshaking control signal, and a logical AND gate for generating an in-block clock based on the stop signal having the negative logic which is output from the transfer control section and the system clock.

Abstract: It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase in a design period by circuit tuning. A local block control circuit comprises an end detecting section for receiving a plurality of complete signals, a transfer control section for generating a stop signal having a negative logic to determine whether or not a system clock is supplied to a processing block upon receipt of an end signal output from the end detecting section, the system clock and a handshaking control signal, and a logical AND gate for generating an in-block clock based on the stop signal having the negative logic which is output from the transfer control section and the system clock.

Abstract: In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal lines of the same buses transmit signals changed substantially at the same timing. Thus, cross-talk noise between signal lines can be reduced without widening a bus line pitch.

Abstract: A transfer circuit includes a plurality of cascaded latch circuits. Two consecutive latch circuits in the transfer circuit complementarily enter a latching state and a transparent state in response to the applied clock signal, and data/a signal is transferred through the transfer circuit in response to the clock signal. A clock control circuit is provided for controlling an operation of each of the latch circuits. The clock control circuit detects that the latch circuit in a next stage of the corresponding latch circuit enters the latching state to permits transfer of the signal/data of the corresponding latch circuit to the subsequent stage in accordance with the corresponding clock signal. It is possible to prevent the data/signal from being transferred while the latch circuit at the next stage is in the transparent state to accurately transfer the data/signal. A clock synchronous data transfer and processing device reliably preventing racing is implemented with a simple circuit configuration.

Abstract: In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal lines of the same buses transmit signals changed substantially at the same timing. Thus, cross-talk noise between signal lines can be reduced without widening a bus line pitch.

Abstract: In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal lines of the same buses transmit signals changed substantially at the same timing. Thus, cross-talk noise between signal lines can be reduced without widening a bus line pitch.

Abstract: It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase in a design period by circuit tuning. A local block control circuit comprises an end detecting section for receiving a plurality of complete signals, a transfer control section for generating a stop signal having a negative logic to determine whether or not a system clock is supplied to a processing block upon receipt of an end signal output from the end detecting section, the system clock and a handshaking control signal, and a logical AND gate for generating an in-block clock based on the stop signal having the negative logic which is output from the transfer control section and the system clock.

Abstract: A transfer circuit includes a plurality of cascaded latch circuits. Two consecutive latch circuits in the transfer circuit complementarily enter a latching state and a transparent state in response to the applied clock signal, and data/a signal is transferred through the transfer circuit in response to the clock signal. A clock control circuit is provided for controlling an operation of each of the latch circuits. The clock control circuit detects that the latch circuit in a next stage of the corresponding latch circuit enters the latching state to permits transfer of the signal/data of the corresponding latch circuit to the subsequent stage in accordance with the corresponding clock signal. It is possible to prevent the data/signal from being transferred while the latch circuit at the next stage is in the transparent state to accurately transfer the data/signal. A clock synchronous data transfer and processing device reliably preventing racing is implemented with a simple circuit configuration.

Abstract: A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS transistor between a line of a potential higher than the ground potential by a threshold voltage and the bus line. The potential of the bus line is limited between the level of the power supply potential and the ground potential, so that the noise level of the bus line is reduced.

Abstract: In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal lines of the same buses transmit signals changed substantially at the same timing. Thus, cross-talk noise between signal lines can be reduced without widening a bus line pitch.

Abstract: A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS transistor between a line of a potential higher than the ground potential by a threshold voltage and the bus line. The potential of the bus line is limited between the level of the power supply potential and the ground potential, so that the noise level of the bus line is reduced.

Abstract: A clock driver formation region in which clock drivers are formed is disposed in a position overlapping, in a plan view, with a ring interconnection line and a mesh interconnection line extending over a semiconductor substrate region. An extra region dedicated to the clock driver formation region is not required, and the clock drivers are dispersed in a circuit device. Therefore, by adjusting drive capabilities of the clock drivers, a clock skew can be reduced, and electromagnetic noises during operation of the clock driver can be absorbed by interconnection lines at a higher layer.

Abstract: A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.

Abstract: A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.

Abstract: A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved, and the data output is executed in a predetermined order.

Abstract: A data retrieving apparatus comprising an address an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in resp

Abstract: An improved self-timed pipeline processor is provided with self-timed data transfer, thereby making it possible to control exclusively the memory reading and memory writing accesses of individual pipeline stages. The self-timed pipeline processor prohibits memory reading during memory writing and vice versa. In addition, the pipeline processor temporarily prevents the transfer of data to a next-accessing pipeline stage when the memory address presently being accessed is the same as the address to be accessed next, thereby preventing malfunction of the processor.

Abstract: A data retrieving apparatus having an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the res

Abstract: A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved and the data output is executed in a predetermined order.

Abstract: A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a backward path of the same, and a loop-back part therebetween, and comprises bypasses between the shift register on the forward path and on the backward path to bypass the transmitted data when significant data does not exist on the loop-back part side from a stage on which the bypass is comprised and no data stays at a stage where the bypass is comprised, so that data is transmitted at high speed, and which is constructed to be able to control the bypass from external, so that testing of circuitry is easy.