Abstract: A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

Abstract: In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.

Abstract: An improved data driven processor that utilizes queue buffers in the data path to maintain optimal dataflow.

Abstract: A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer request signal changes from an active to an inactive status. The second control signal is coupled to an input of the NAND gate and inactivates the first control signal. Thus, data transfer cannot recur until after the data transfer request signal changes to an inactive status so that parasitic oscillations are eliminated. The flip-flop consists of two, two input NAND gates that are located out of the path of data transfer and that are easier to fabricate than the prior art D flip-flop.