Abstract: A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.

Abstract: Provided is a transmission system with increased degree of freedom in a lane configuration, which corrects disalignment of data sequences in respective channels due to differences in arrival time, thereby freely changing a number of lanes. The transmission system includes: a transmitter; a relay; and a receiver, the transmitter inputting data to be transmitted to the receiver, the relay transmitting the data transmitted by the transmitter to the receiver, the receiver receiving the data transmitted by the relay. The transmitter inserts into the data sequences channel information indicating a channel to which the data sequence is to be output. The relay corrects, based on the channel information, disalignment in an order of arrival of the data sequences received via a plurality of channels, the disalignment being generated by the differences in arrival time of the data sequences among the channels.

Abstract: It is provided a data transmission system comprising a transmitter, a repeater and a receiver. The transmitter and the repeater are coupled through a first transmission path and the receiver and the repeater are coupled through a second transmission path. The transmitter, the repeater and the receiver have virtual lanes. The transmitter demultiplexes the transmission data into as many data streams as a number of useable virtual lanes based on useable lane information. The repeater monitors failures of the transmission lanes of the first transmission path and the virtual lanes. The receiver monitors failures of the transmission lanes of the second transmission path and the virtual lanes, selects the useable virtual lanes, sends to the transmitter the useable lane information, corrects a wrong order of the received data streams and a shift of reception point in the virtual lanes, and restores the demultiplexed data streams into the transmission data.

Abstract: In a method for data transmission, which transmits data through a transmission line, which integrates a plurality of links into one transmission line, a first link group, which transmits information data by at least one link out of a plurality of links, a second link group, which transmits parity data generated by the information data by at least one link out of a plurality of links, which are different from the first link group, and a third link group, which generates an error check data related to an error correction from the information data or the parity data, when an error occurs in the information data or the parity data, and transmits by at least one link out of a plurality of links, which are different from the first link group and the second link group, are integrated and transmitted.

Abstract: A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.

Abstract: Provided is a transmission system with increased degree of freedom in a lane configuration, which corrects disalignment of data sequences in respective channels due to differences in arrival time, thereby freely changing a number of lanes. The transmission system includes: a transmitter; a relay; and a receiver, the transmitter inputting data to be transmitted to the receiver, the relay transmitting the data transmitted by the transmitter to the receiver, the receiver receiving the data transmitted by the relay. The transmitter inserts into the data sequences channel information indicating a channel to which the data sequence is to be output. The relay corrects, based on the channel information, disalignment in an order of arrival of the data sequences received via a plurality of channels, the disalignment being generated by the differences in arrival time of the data sequences among the channels.

Abstract: A data transmission system comprising a transmitter and a receiver. The transmitter comprises a phase encoder for partitioning consecutive bit data to be input in data in units of X bits; and converting a 2x value indicated by the data of X bits in unique association with an (N/2-1)Y value of a Y symbol, and for confining use of signal points, from among the signal points of N-ary phase, only to a signal point P1 (at a phase angle 0) and N/2-2 signal points P(2n+2) (where 1?n<N/2-2). The receiver comprises a phase decoder for notifying an error detection when a signal point other than a signal point that are permitted to be used is received, and performing an error correction by changing the signal point to a signal point which has a smaller hamming distance.

Abstract: In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.

Abstract: A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.

Abstract: In a method for data transmission, which transmits data through a transmission line 20, which integrates a plurality of links into one transmission line, a first link group, which transmits information data by at least one link out of a plurality of links, a second link group, which transmits parity data generated by the information data by at least one link out of a plurality of links, which are different from the first link group, and a third link group, which generates an error check data related to an error correction from the information data or the parity data, when an error occurs in the information data or the parity data, and transmits by at least one link out of a plurality of links, which are different from the first link group and the second link group, are integrated and transmitted.

Abstract: A Packet communication system has a first line interface; a second line interface that accommodates lines slower than lines accommodated by the first line interface; a crossbar switch; and a scheduler that periodically receives packet output requests from the first and second line interfaces and sends grants based on the requests for the crossbar switch to the first and second line interfaces. The link capacity between the first line interface and the crossbar switch is made higher than that between the second line interface and the crossbar switch, whereby a packet communication system capable of accommodating line interfaces with different speeds efficiently can be provided.

Abstract: Provided is a transversal filter, in which delayers and multipliers are connected in series, includes: a first multiplier for multiplying a first tap coefficient set by a tap coefficient register module and an input signal to output a result of multiplication; a first delayer for delaying the value output from the first multiplier by a predetermined time to output the delayed value; a second multiplier for multiplying a second tap coefficient set by the tap coefficient register module and an input signal to output a result of multiplication; a first adder for adding the value output from the delayer situated upstream to the value output from the second multiplier to output a result of addition; a second delayer for delaying the value output from the first adder by a predetermined time to output the delayed value; and a selector for selecting one of the input signal, the value output from the first delayer, and the value output from the second delayer to output the selected one.

Abstract: In a high-speed serial-to-parallel conversion transmission system, a transmitter inserts pattern data composed of a combination of a plurality of idle characters in a signal to be transmitted such that a receiver measures an amount of skew, while the receiver measures the amount of skew and performs delay control over the received signal. By using the idle characters as the pattern data, a skew compensation pattern can be inserted as invalid data in a transmitted data stream containing valid data.

Abstract: A packet switching system arbitrates between Virtual Output Queues (VoQ) in plural input buffers, so as to grant the right of transmitting data to a crossbar switch to some of the VoQs by taking both an output data interval of a VoQ and the queue length of a VoQ as parameters. The system suppresses the delay time of the segment of a VoQ having a high load, thereby preventing buffers from overflowing; and, also, the system permits a VoQ having a low load to transmit segments under no influence of the VoQ that has a high load and is just reading out the segment.

Abstract: Disclosed is a data transmission device of variable communication capacity that can set bands and set line communication capacities according to users' requests, and can automatically determine usable lines. The data transmission device includes: a transmission device having a transmission unit connected to N (N>1) transmission lines; a reception device having a reception unit connected to N reception lines; and negotiation units connected to both the transmission unit and the reception unit. The transmission unit converts transmission data of parallel bits into a data array with one to N trains that is different in the number of data trains depending on specified transmission capacity. The reception unit synthesizes reception data trains inputted from one to N reception lines determined by specified reception capacity, of the N reception lines.

Abstract: A packet switch has a switch section formed by a plurality of crossbar switch planes and plurality of interfaces, and each interface outputs in parallel input packets in block units to the plurality of crossbar switch planes in response to signals from a scheduler, wherein when n crossbar switch planes can be mounted on the packet switch, each interface allocates time slots corresponding to the n crossbar switch planes or when a switch plane is additionally mounted, a block is read at a time slot corresponding to the additional switch plane or when a switch plane is stopped from working, an idle time slot is used to prevent a block from being output to the switch plane which is unused.

Abstract: In a high-speed serial-to-parallel conversion transmission system, a transmitter inserts pattern data composed of a combination of a plurality of idle characters in a signal to be transmitted such that a receiver measures an amount of skew, while the receiver measures the amount of skew and performs delay control over the received signal. By using the idle characters as the pattern data, a skew compensation pattern can be inserted as invalid data in a transmitted data stream containing valid data.

Abstract: A switching node (MGS) 1 connected to a relay network 5 has a table 37 prestoring bandwidth control parameter values in correspondence with the size of data transferred via the relay network. When a request for accessing a remote storage apparatus is received, the switching node obtains the bandwidth control parameter values adapted to the transfer data size indicated by the access request are obtained from the table 37, and automatically sets a path having an optimum bandwidth on the relay network by using the parameter values. The path is automatically released when the data transfer is finished.

Abstract: A Packet communication system according to the present invention comprises a first line interface; a second line interface that accommodates lines slower than lines accommodated by the first line interface; a crossbar switch; and a scheduler that periodically receives packet output requests from the first and second line interfaces, and sends grants based on the requests for the crossbar switch to the first and second line interfaces; the link capacity between the first line interface and the crossbar switch is made higher than that between the second line interface and the crossbar switch, whereby a packet communication system capable of accommodating line interfaces with different speeds efficiently can be provided.

Abstract: A packet switching system that arbitrates between Virtual Output Queues (VoQ) in plural input buffers, so as to grant the right of transmitting data to a crossbar switch to some of the VoQs by taking both an output data interval of VoQ and queue length of VoQ as parameters, wherein the system suppresses the delay time of the segment of VoQ having high load thereby preventing buffers from overflowing; and also permits the VoQ having low loads to transmit segments under no influence of the VoQ that has high load and is just reading out the segment.