Abstract: Provided are a hydrocarbon adsorbent, an exhaust gas purifying catalyst, and an exhaust gas purifying system, which are capable of adsorbing hydrocarbons, storing the adsorbed hydrocarbons up to a relatively high temperature, and desorbing the adsorbed and stored hydrocarbons at a relatively high temperature. The hydrocarbon adsorbent contains a multipore zeolite containing, outside the zeolite framework, at least one metal selected from the group consisting of transition metals belonging to Groups 3 to 12 in the periodic table, amphoteric metals belonging to Groups 13 and 14 in the periodic table, alkali metals, and alkaline earth metals; and has a content ratio of the metal of 9% by mass or less relative to the multipore zeolite containing the metal.

Abstract: Provided are: a hydrocarbon adsorbent capable of adsorbing hydrocarbons, storing the adsorbed hydrocarbons up to a relatively high temperature, and desorbing the adsorbed and stored hydrocarbons at a relatively high temperature; an exhaust gas purifying catalyst composition using the same; an exhaust gas purifying catalyst; and a method for treating an exhaust gas. The hydrocarbon adsorbent comprises a zeolite having an MRT-type framework structure. The hydrocarbon adsorbent comprises a small-pore zeolite having a total desorption amount ZD1 of propylene desorbed at 50° C. or higher and lower than 300° C. being 3.5 mmol/g or less and a total desorption amount ZD2 of propylene desorbed at 300° C. or higher and 500° C. or lower being 0.5 mmol/g or more, per 1 g by mass of the small-pore zeolite, when adsorbing propylene at 50° C. and then heating from 50° C. to 500° C. under the condition of 10° C./min by a temperature-programmed desorption method.

Abstract: Provided are: an exhaust gas purifying composition that contains a phosphorus-containing BEA-type zeolite and has further improved heat resistance; and a production method therefor. The exhaust gas purifying composition contains a phosphorus-containing BEA-type zeolite, wherein the phosphorus-containing BEA-type zeolite has a pore volume ratio (V2/V1) of a micropore volume V2 having a pore diameter in a range of 2 nm or less, as measured by a SF method, to a mesopore volume V1 having a pore diameter in a range of 2 nm or more and 100 nm or less, as measured by a BJH method, of 2.0 or more.

Abstract: To provide a numerical simulation apparatus capable of executing a numerical simulation with high speed and precision by reducing computational complexity. A numerical simulation apparatus that executes a numerical simulation using a wave function which is a solution of a time dependent Schrödinger equation includes: a real time evolution calculation unit that calculates a second wave function while evolving the second wave function from an initial time in increments of a predetermined time period, the second wave function being obtained by applying a central difference approximation in a real-space finite-difference method to a first wave function expressed using a propagator, and being expressed using a Bessel function; and a calculation result storage unit that stores a calculation result of the second wave function obtained at each time by the time evolution calculation unit while evolving the second wave function in increments of the predetermined time period.

Abstract: To provide a numerical simulation apparatus capable of executing a numerical simulation with high speed and precision by reducing computational complexity. A numerical simulation apparatus (100) that executes a numerical simulation using a wave function which is a solution of a time dependent Schrödinger equation includes: a real time evolution calculation unit (106) that calculates a second wave function while evolving the second wave function from an initial time in increments of a predetermined time period, the second wave function being obtained by applying a central difference approximation in a real-space finite-difference method to a first wave function expressed using a propagator, and being expressed using a Bessel function; and a calculation result storage unit (108) that stores a calculation result of the second wave function obtained at each time by the time evolution calculation unit (106) while evolving the second wave function in increments of the predetermined time period.

Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: An electrode for electrolytic processing has a conductive material and an organic compound having an ion exchange group. The organic compound is chemically bonded to a surface of the conductive material. The organic compound comprises thiol or disulfide. The ion exchange group comprises at least one of a sulfo group, a carboxyl group, a quaternary ammonium group, and an amino group. The conductive material includes at least one of gold, silver, platinum, copper, gallium arsenide, cadmium sulfide, and indium oxide (III).

Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.

Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.

Abstract: To prevent Al wiring formed on a via-hole in which a CVD-TiN film is embedded from corroding.

Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: [Object] To prevent Al wiring formed on a via-hole in which a CVD-TiN film is embedded from corroding.