Patents by Inventor Hidekazu Goto

Hidekazu Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240367145
    Abstract: An exhaust gas purification catalyst including: a substrate; and an adsorbent portion provided to the substrate and containing a Si-containing adsorbent material. The adsorbent portion includes a plurality of voids, and in a cross section orthogonal to an exhaust gas flow direction, the percentage of a total area of the voids that are present in the adsorbent portion and that each satisfy the expression below is greater than 5% to 30% or less with respect to an apparent area of the adsorbent portion present on the substrate. Expression: L/{2(?S)½}?1.1. (L is a perimeter of the void in the cross section, and S is an area of the void in the cross section.
    Type: Application
    Filed: October 4, 2022
    Publication date: November 7, 2024
    Inventors: Yoshinori ENDO, Momoka YAMANAKA, Hidekazu GOTO, Takashi BABA
  • Publication number: 20240190881
    Abstract: Provided are: a pyrrolidine derivative containing quaternary ammonium cations having a bicyclo framework that can be used as an organic structure directing agent; a method for producing the same; an MSE-type zeolite; and a method for producing the same. The pyrrolidine derivative containing quaternary ammonium cations having a bicyclo framework has, in an X-ray diffraction spectrum, a highest peak intensity I in a diffraction angle (2?) range of 14.0° to 16.0° and a highest peak intensity II in a diffraction angle (2?) range of 17.0° to 19.0°, wherein a peak intensity ratio (I/II) of the peak intensity I to the peak intensity II is in a range of 0.4 or more and 1.5 or less.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 13, 2024
    Inventors: Katsuhiko HAYASHI, Kenji TAMURA, Satoshi MOGI, Susumu TAKAHASHI, Hidekazu GOTO
  • Publication number: 20240170327
    Abstract: An apparatus includes: a first semiconductor substrate; a plurality of first regions extending in parallel in a first direction on the first semiconductor substrate, each of the plurality of first regions including a plurality of first shallow trench isolations (STI) therein; and a plurality of second regions each extending between corresponding adjacent two of the plurality of first regions, each of the plurality of second regions including a plurality of second STIs and a plurality of active regions arranged alternately and in line in the first direction. Each of the plurality of second STIs has a greater depth than each of the plurality of first STIs.
    Type: Application
    Filed: September 5, 2023
    Publication date: May 23, 2024
    Applicant: Micron Technology, Inc.
    Inventors: MITSUNARI SUKEKAWA, HIDEKAZU GOTO, SHINICHI NAKATA
  • Publication number: 20230271136
    Abstract: Provided are a hydrocarbon adsorbent, an exhaust gas purifying catalyst, and an exhaust gas purifying system, which are capable of adsorbing hydrocarbons, storing the adsorbed hydrocarbons up to a relatively high temperature, and desorbing the adsorbed and stored hydrocarbons at a relatively high temperature. The hydrocarbon adsorbent contains a multipore zeolite containing, outside the zeolite framework, at least one metal selected from the group consisting of transition metals belonging to Groups 3 to 12 in the periodic table, amphoteric metals belonging to Groups 13 and 14 in the periodic table, alkali metals, and alkaline earth metals; and has a content ratio of the metal of 9% by mass or less relative to the multipore zeolite containing the metal.
    Type: Application
    Filed: July 29, 2021
    Publication date: August 31, 2023
    Inventors: Hidekazu GOTO, Katsuhiko HAYASHI, Mayuko SUWA
  • Publication number: 20230049498
    Abstract: Provided are: a hydrocarbon adsorbent capable of adsorbing hydrocarbons, storing the adsorbed hydrocarbons up to a relatively high temperature, and desorbing the adsorbed and stored hydrocarbons at a relatively high temperature; an exhaust gas purifying catalyst composition using the same; an exhaust gas purifying catalyst; and a method for treating an exhaust gas. The hydrocarbon adsorbent comprises a zeolite having an MRT-type framework structure. The hydrocarbon adsorbent comprises a small-pore zeolite having a total desorption amount ZD1 of propylene desorbed at 50° C. or higher and lower than 300° C. being 3.5 mmol/g or less and a total desorption amount ZD2 of propylene desorbed at 300° C. or higher and 500° C. or lower being 0.5 mmol/g or more, per 1 g by mass of the small-pore zeolite, when adsorbing propylene at 50° C. and then heating from 50° C. to 500° C. under the condition of 10° C./min by a temperature-programmed desorption method.
    Type: Application
    Filed: March 11, 2021
    Publication date: February 16, 2023
    Inventors: Mayuko SUWA, Hidekazu GOTO
  • Publication number: 20220258123
    Abstract: Provided are: an exhaust gas purifying composition that contains a phosphorus-containing BEA-type zeolite and has further improved heat resistance; and a production method therefor. The exhaust gas purifying composition contains a phosphorus-containing BEA-type zeolite, wherein the phosphorus-containing BEA-type zeolite has a pore volume ratio (V2/V1) of a micropore volume V2 having a pore diameter in a range of 2 nm or less, as measured by a SF method, to a mesopore volume V1 having a pore diameter in a range of 2 nm or more and 100 nm or less, as measured by a BJH method, of 2.0 or more.
    Type: Application
    Filed: June 5, 2020
    Publication date: August 18, 2022
    Inventors: Hidekazu GOTO, Jo NISHIKAWA, Mayuko SUWA
  • Patent number: 8374827
    Abstract: To provide a numerical simulation apparatus capable of executing a numerical simulation with high speed and precision by reducing computational complexity. A numerical simulation apparatus that executes a numerical simulation using a wave function which is a solution of a time dependent Schrödinger equation includes: a real time evolution calculation unit that calculates a second wave function while evolving the second wave function from an initial time in increments of a predetermined time period, the second wave function being obtained by applying a central difference approximation in a real-space finite-difference method to a first wave function expressed using a propagator, and being expressed using a Bessel function; and a calculation result storage unit that stores a calculation result of the second wave function obtained at each time by the time evolution calculation unit while evolving the second wave function in increments of the predetermined time period.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: February 12, 2013
    Assignee: Osaka University
    Inventors: Kikuji Hirose, Hidekazu Goto
  • Publication number: 20090204375
    Abstract: To provide a numerical simulation apparatus capable of executing a numerical simulation with high speed and precision by reducing computational complexity. A numerical simulation apparatus (100) that executes a numerical simulation using a wave function which is a solution of a time dependent Schrödinger equation includes: a real time evolution calculation unit (106) that calculates a second wave function while evolving the second wave function from an initial time in increments of a predetermined time period, the second wave function being obtained by applying a central difference approximation in a real-space finite-difference method to a first wave function expressed using a propagator, and being expressed using a Bessel function; and a calculation result storage unit (108) that stores a calculation result of the second wave function obtained at each time by the time evolution calculation unit (106) while evolving the second wave function in increments of the predetermined time period.
    Type: Application
    Filed: September 7, 2007
    Publication date: August 13, 2009
    Inventors: Kikuji Hirose, Hidekazu Goto
  • Publication number: 20070148896
    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
    Type: Application
    Filed: November 27, 2006
    Publication date: June 28, 2007
    Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
  • Patent number: 7224016
    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: May 29, 2007
    Assignees: Elpida Memory, Inc., Hitachi ULSI Systems, Co., Ltd., Hitachi Ltd.
    Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
  • Patent number: 7183170
    Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 27, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Kawagoe, Hiroshi Sakuma, Isamu Asano, Keiji Kuroki, Hidekazu Goto, Shinpei Iijima
  • Patent number: 7119443
    Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: October 10, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Publication number: 20050183963
    Abstract: An electrode for electrolytic processing has a conductive material and an organic compound having an ion exchange group. The organic compound is chemically bonded to a surface of the conductive material. The organic compound comprises thiol or disulfide. The ion exchange group comprises at least one of a sulfo group, a carboxyl group, a quaternary ammonium group, and an amino group. The conductive material includes at least one of gold, silver, platinum, copper, gallium arsenide, cadmium sulfide, and indium oxide (III).
    Type: Application
    Filed: March 10, 2005
    Publication date: August 25, 2005
    Inventors: Yuzo Mori, Hidekazu Goto, Yasushi Toma
  • Publication number: 20050118762
    Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 2, 2005
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Kawagoe, Hiroshi Sakuma, Isamu Asano, Keiji Kuroki, Hidekazu Goto, Shinpei Iijima
  • Publication number: 20050040452
    Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
    Type: Application
    Filed: October 7, 2004
    Publication date: February 24, 2005
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Patent number: 6853081
    Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: February 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Publication number: 20040248362
    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
    Type: Application
    Filed: February 13, 2004
    Publication date: December 9, 2004
    Applicants: ELPIDA MEMORY, INC., Hitachi ULSI Systems, Co., Ltd., HITACHI LTD.
    Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
  • Patent number: 6686619
    Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: February 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Hideo Aoki, Yoshikazu Ohira, Tadashi Umezawa, Satoru Yamada, Keizou Kawakita, Isamu Asano, Naoki Fukuda, Tsuyoshi Tamaru, Hidekazu Goto, Nobuyoshi Kobayashi
  • Publication number: 20030211673
    Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.
    Type: Application
    Filed: June 6, 2003
    Publication date: November 13, 2003
    Inventors: Yoshitaka Nakamura, Hideo Aoki, Yoshikazu Ohira, Tadashi Umezawa, Satoru Yamada, Keizou Kawakita, Isamu Asano, Naoki Fukuda, Tsuyoshi Tamaru, Hidekazu Goto, Nobuyoshi Kobayashi
  • Publication number: 20030205811
    Abstract: To prevent Al wiring formed on a via-hole in which a CVD-TiN film is embedded from corroding.
    Type: Application
    Filed: June 4, 2003
    Publication date: November 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa