Patents by Inventor Hidekazu Goto

Hidekazu Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030064578
    Abstract: [Object] To prevent Al wiring formed on a via-hole in which a CVD-TiN film is embedded from corroding.
    Type: Application
    Filed: November 5, 2002
    Publication date: April 3, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Patent number: 6492730
    Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: December 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Publication number: 20020182798
    Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 5, 2002
    Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
  • Publication number: 20020123190
    Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.
    Type: Application
    Filed: May 3, 2002
    Publication date: September 5, 2002
    Inventors: Yoshitaka Nakamura, Hideo Aoki, Yoshikazu Ohira, Tadashi Umezawa, Satoru Yamada, Keizou Kawakita, Isamu Asano, Naoki Fukuda, Tsuyoshi Tamaru, Hidekazu Goto, Nobuyoshi Kobayashi
  • Patent number: 6399438
    Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: June 4, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
  • Publication number: 20020047153
    Abstract: A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.
    Type: Application
    Filed: October 30, 2001
    Publication date: April 25, 2002
    Inventors: Yoshitaka Nakamura, Hideo Aoki, Yoshikazu Ohira, Tadashi Umezawa, Satoru Yamada, Keizou Kawakita, Isamu Asano, Naoki Fukuda, Tsuyoshi Tamaru, Hidekazu Goto, Nobuyoshi Kobayashi
  • Patent number: 6329681
    Abstract: A semiconductor integrated circuit device and a method of manufacturing such a device provides the advantages that undulations are prevented from being produced in the polycrystal silicon plugs in the bit line contact holes and that the undesired phenomenon of transversally etching the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines BL formed at the time of forming a first wiring layer 18 is made of a laminate film having a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c and a titanium silicide film 20 containing nitrogen or oxygen is formed in the contact areas of the bit lines BL and the plugs 19. A titanium silicide film 20 containing nitrogen or oxygen is also formed in the contact areas of the first wiring layer 18 and the semiconductor substrate 1.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: December 11, 2001
    Inventors: Yoshitaka Nakamura, Hideo Aoki, Yoshikazu Ohira, Tadashi Umezawa, Satoru Yamada, Keizou Kawakita, Isamu Asano, Naoki Fukuda, Tsuyoshi Tamaru, Hidekazu Goto, Nobuyoshi Kobayashi
  • Publication number: 20010023099
    Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
    Type: Application
    Filed: April 9, 2001
    Publication date: September 20, 2001
    Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
  • Patent number: 6215144
    Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: April 10, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
  • Patent number: 6028360
    Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
  • Patent number: 5177589
    Abstract: In forming a metal or metal silicide film by CVD, a fluoro-silane is used as a reaction gas, or a fluoro-silane is added to a source gas. Examples of the metal halide used in the present invention include fluorides and chlorides of tungsten, molybdenum, titanium, tantalum and niobium. Among them, fluorides of tungsten and molybdenum are more desirable particularly from the viewpoint of the availability of the deposited metal or metal silicide. It is preferred that the source gases, i.e. silane series gas and metal halide, be diluted with a carrier gas such as nitrogen, hydrogen, helium or argon, and this is also true of the fluoro-silane. The total pressure is preferably 0.01 to 10 Torr. The reaction temperature is desirably 200.degree. to 800.degree. C., more desirably 300.degree. to 500.degree. C. Plasma CVD instead of thermal CVD may be employed for the purpose of lowering the reaction temperature.
    Type: Grant
    Filed: September 25, 1991
    Date of Patent: January 5, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyoshi Kobayashi, Hidekazu Goto, Masayuki Suzuki, Yoshio Homma, Natsuki Yokoyama, Yoshitaka Nakamura
  • Patent number: 5175017
    Abstract: In forming a metal or metal silicide film by CVD, a fluorosilane is used as a reaction gas, or a fluoro-silane is added to a source gas. Examples of the metal halide used in the present invention include fluorides and chlorides of tungsten, molybdenum, titanium, tantalum and niobium. Among them, fluorides of tungsten and molybdenum are more desirable particularly from the viewpoint of the availability of the deposited metal or metal silicide. It is preferred that the source gases, i.e. silane series gas and metal halide, be diluted with a carrier gas such as nitrogen, hydrogen, helium or argon, and this is also true of the fluoro-silane. The total pressure is preferably 0.01 to 10 Torr. The reaction temperature is desirably 200.degree. to 800.degree. C., more desirably 300.degree. to 500.degree. C. Plasma CVD instead of thermal CVD may be employed for the purpose of lowering the reaction temperature.
    Type: Grant
    Filed: January 28, 1991
    Date of Patent: December 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyoshi Kobayashi, Hidekazu Goto, Masayuki Suzuki, Yoshio Homma, Natsuki Yokoyama