Abstract: A scan control method for a circuit device connected with a first bus and having a test access port controller, including setting information indicating a register to be scanned in the circuit device, a number of scan shifts and a scan start via a second bus different from the first bus, and generating based on the information set, by using a sequencer, a signal replacing a test mode signal and a test reset signal transferred via the first bus during testing of the circuit device, and supplying the signal to the test access port controller.

Abstract: The frequency of the internal clock is set at ½ of the frequency of an external clock as well as the width of the internal bus is configured to be twice as wide as the width of an external bus. A write control unit controls a bypass unit and a swap circuit unit and, when a plurality of packets are received, writes words of the packets such that headers H of the received packets are respectively arranged alternately in each packet storage sector between an even-numbered queue and an odd-numbered queue. A read control unit reads the words of the packets in parallel by two words at each time from the even-numbered queue and the odd-numbered queue.

Abstract: A system transmits a data packet from a transmitting apparatus to a receiving apparatus. The receiving apparatus includes a receive buffer, and a size specifying information transmitting unit that transmits size specifying information to the transmitting apparatus. The transmitting apparatus includes a transmit buffer, a credit storage unit that stores, as a credit, a value corresponding to a total size of all data packets stored in the receive buffer, a credit adding unit that adds a credit to the stored credit on transmitting a data packet, a credit subtracting unit that specifies a size of a read-out data packet on receiving the size specifying information, subtracts a credit corresponding to the specified size from a stored credit, and a transmission controlling unit that controls data packet transmission based on a credit stored in the credit storage unit.

Abstract: A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plurality of data signals is changed.

Abstract: A mutual electrically connecting part mutually connects a plurality of information processing parts, wherein the mutual connecting part comprises a phase adjusting part configured to adjust a phase from each of the respective ones of the plurality of information processing parts; and the mutual connecting part further has a power supply cut signal transmitting part transmitting a power supply cut signal, indicating that power supply to any one of the plurality of information processing parts is cut, to the phase adjusting part corresponding to the information processing part; and an initializing part initializing the phase adjusting part corresponding to the information proceeding part for which power supply is cut, in response to the transmission of the power supply cut signal from the power supply cut signal transmitting part.

Abstract: The frequency of the internal clock is set at ½ of the frequency of an external clock as well as the width of the internal bus is configured to be twice as wide as the width of an external bus. A write control unit controls a bypass unit and a swap circuit unit and, when a plurality of packets are received, writes words of the packets such that headers H of the received packets are respectively arranged alternately in each packet storage sector between an even-numbered queue and an odd-numbered queue. A read control unit reads the words of the packets in parallel by two words at each time from the even-numbered queue and the odd-numbered queue.

Abstract: A crossbar includes input queue groups and a distribution processor. The input queue groups include multi-step input queues of data packets whose data transmission destinations are “address W” and “address Y” or “address X” and “address Z” and are provided respectively at input ports A and B and input ports C and D. The distribution processor distributes the data packet input into the input port to input queue group according to the data transmission destinations (that is, “address W”, “address Y”, “address X”, and “address Z”) of the input data.