Abstract: A method for manufacturing a composite structure includes: an application step including providing a bonding material on a base member by applying a metal paste onto the base member; a preheating step including heating the bonding material before an element to be bonded is stacked on the bonding material and thereby drying the bonding material until a percentage of an organic component in the bonding material becomes 3% by mass and equal to or less than 8% by mass with respect to the bonding material; a mounting step including stacking the element to be bonded onto the bonding material and heating the bonding material to form a multi-layer stack; and a sintering step including sintering the bonding material by heating the multi-layer stack in a heating furnace and thereby forming the bonding layer.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

Abstract: A bidirectional switch includes: a first lateral transistor including a first semiconductor layer on the surface of a first conductive layer; a second lateral transistor including a second semiconductor layer on the surface of a second conductive layer; a connection member; a first conductor member; and a second conductor member. The connection member connects the first lateral transistor and the second lateral transistor together in anti-series. The first conductor member electrically connects the first source electrode of the first lateral transistor to the first conductive layer. The second conductor member electrically connects the second source electrode of the second lateral transistor to the second conductive layer.

Abstract: A bidirectional switch includes: a first lateral transistor including a first semiconductor layer on the surface of a first conductive layer; a second lateral transistor including a second semiconductor layer on the surface of a second conductive layer; a connection member; a first conductor member; and a second conductor member. The connection member connects the first lateral transistor and the second lateral transistor together in anti-series. The first conductor member electrically connects the first source electrode of the first lateral transistor to the first conductive layer. The second conductor member electrically connects the second source electrode of the second lateral transistor to the second conductive layer.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A bidirectional switch includes a semiconductor element and a substrate potential stabilizer which stabilizes a substrate potential of a semiconductor element. The substrate potential stabilizer includes a first switch element and a second switch element. Both the first switch element and the second switch element are on when the semiconductor element is on.

Abstract: A bidirectional switch includes a semiconductor element and a substrate potential stabilizer which stabilizes a substrate potential of a semiconductor element. The substrate potential stabilizer includes a first switch element and a second switch element. Both the first switch element and the second switch element are on when the semiconductor element is on.

Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.

Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.

Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 ?cm or more, and the internal region has a resistivity of 1000 ?cm or more.

Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.

Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.