Patents by Inventor Hidekazu Umeda

Hidekazu Umeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150171173
    Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 ?cm or more, and the internal region has a resistivity of 1000 ?cm or more.
    Type: Application
    Filed: March 2, 2015
    Publication date: June 18, 2015
    Inventors: HIDEKAZU UMEDA, MASAHIRO ISHIDA, TETSUZO UEDA, DAISUKE UEDA
  • Patent number: 8884332
    Abstract: A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Umeda, Tetsuzo Ueda, Daisuke Ueda
  • Patent number: 8872227
    Abstract: A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: October 28, 2014
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Umeda, Yoshiharu Anda, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20140097433
    Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 10, 2014
    Applicant: Panasonic Corporation
    Inventors: Noboru NEGORO, Hidekazu UMEDA, Nanako HIRASHITA, Tetsuzo UEDA
  • Patent number: 8692292
    Abstract: A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm?3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Umeda, Tetsuzo Ueda
  • Publication number: 20130341682
    Abstract: A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Hidekazu UMEDA, Tetsuzo UEDA, Daisuke UEDA
  • Patent number: 8569797
    Abstract: A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 29, 2013
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Umeda, Masahiro Hikita, Tetsuzo Ueda
  • Patent number: 8390029
    Abstract: A semiconductor device includes an undoped GaN layer (103) formed on a substrate (101), an undoped AlGaN layer (104) formed on the undoped GaN layer (103) and having a band gap energy larger than that of the undoped GaN layer (103), a p-type AlGaN layer (105) and a high-concentration p-type GaN layer (106) formed on the undoped AlGaN layer (104), and an n-type AlGaN layer (107) formed on the high-concentration p-type GaN layer (106). A gate electrode (112) which makes ohmic contact with the high-concentration p-type GaN layer (106) is formed on the high-concentration p-type GaN layer (106) in a region thereof exposed through an opening (107a) formed in the n-type AlGaN layer (107).
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Umeda, Masahiro Hikita, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20120153355
    Abstract: A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 21, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Hidekazu UMEDA, Yoshiharu Anda, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20120119261
    Abstract: A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm?3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 17, 2012
    Applicant: Panasonic Corporation
    Inventors: Hidekazu UMEDA, Tetsuzo Ueda
  • Publication number: 20110272740
    Abstract: A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Hidekazu UMEDA, Masahiro HIKITA, Tetsuzo UEDA
  • Patent number: 7959729
    Abstract: A production method is provided in which Group-III-element nitride single crystals that have a lower dislocation density and a uniform thickness and are transparent, high quality, large, and bulk crystals can be produced with a high yield. The method for producing Group-III-element nitride single crystals includes: heating a reaction vessel containing at least one metal element selected from the group consisting of an alkali metal and an alkaline-earth metal and at least one Group III element selected from the group consisting of gallium (Ga), aluminum (Al), and indium (In) to prepare a flux of the metal element; and feeding nitrogen-containing gas into the reaction vessel and thereby allowing the Group III element and nitrogen to react with each other in the flux to grow Group-III-element nitride single crystals, wherein the single crystals are grown, with the flux being stirred by rocking the reaction vessel, for instance.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: June 14, 2011
    Assignee: Osaka University
    Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Hidekazu Umeda
  • Publication number: 20110012173
    Abstract: A semiconductor device includes an undoped GaN layer (103) formed on a substrate (101), an undoped AlGaN layer (104) formed on the undoped GaN layer (103) and having a band gap energy larger than that of the undoped GaN layer (103), a p-type AlGaN layer (105) and a high-concentration p-type GaN layer (106) formed on the undoped AlGaN layer (104), and an n-type AlGaN layer (107) formed on the high-concentration p-type GaN layer (106). A gate electrode (112) which makes ohmic contact with the high-concentration p-type GaN layer (106) is formed on the high-concentration p-type GaN layer (106) in a region thereof exposed through an opening (107a) formed in the n-type AlGaN layer (107).
    Type: Application
    Filed: January 23, 2009
    Publication date: January 20, 2011
    Inventors: Hidekazu Umeda, Masahiro Hikita, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: 7754012
    Abstract: A method for manufacturing Group III nitride crystals with high quality is provided. By the method, a crystal raw material solution and gas containing nitrogen are introduced into a reactor vessel, which is heated, and crystals are grown in an atmosphere of pressure applied thereto. The gas is introduced from a gas supplying device to the reactor vessel through a gas inlet of the reactor vessel, and then is exhausted to the inside of a pressure-resistant vessel through a gas outlet of the reactor vessel. Since the gas is introduced directly to the reactor vessel, impurities attached to the pressure-resistant vessel and the like into the crystal growing site can be prevented. Further, the gas flows through the reactor vessel, to suppress aggregation of an evaporating alkali metal, etc., at the gas inlet and reduce flow of the metal vapor into the gas supplying device.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 13, 2010
    Assignees: Panasonic Corporation
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Hidekazu Umeda, Yasuhito Takahashi
  • Publication number: 20080213158
    Abstract: A manufacturing apparatus of Group III nitride crystals and a method for manufacturing Group III nitride crystals are provided, by which high quality crystals can be manufactured. For instance, crystals are grown using the apparatus of the present invention as follows. A crystal raw material (131) and gas containing nitrogen are introduced into a reactor vessel (120), to which heat is applied by a heater (110), and crystals are grown in an atmosphere of pressure applied thereto. The gas is introduced from a gas supplying device (180) to the reactor vessel (120) through a gas inlet of the reactor vessel, and then is exhausted to the inside of a pressure-resistant vessel (102) through a gas outlet of the reactor vessel. Since the gas is introduced directly to the reactor vessel (120) without passing through the pressure-resistant vessel (102), the mixture of impurities attached to the pressure-resistant vessel (102) and the like into the site of the crystal growth can be prevented.
    Type: Application
    Filed: April 14, 2008
    Publication date: September 4, 2008
    Applicants: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Hidekazu Umeda, Yasuhito Takahashi
  • Patent number: 7381268
    Abstract: A manufacturing apparatus of Group III nitride crystals and a method for manufacturing Group III nitride crystals are provided, by which high quality crystals can be manufactured. For instance, crystals are grown using the apparatus of the present invention as follows. A crystal raw material (131) and gas containing nitrogen are introduced into a reactor vessel (120), to which heat is applied by a heater (110), and crystals are grown in an atmosphere of pressure applied thereto. The gas is introduced from a gas supplying device (180) to the reactor vessel (120) through a gas inlet of the reactor vessel, and then is exhausted to the inside of a pressure-resistant vessel (102) through a gas outlet of the reactor vessel. Since the gas is introduced directly to the reactor vessel (120) without passing through the pressure-resistant vessel (102), the mixture of impurities attached to the pressure-resistant vessel (102) and the like into the site of the crystal growth can be prevented.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: June 3, 2008
    Assignees: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Hidekazu Umeda, Yasuhito Takahashi
  • Publication number: 20070157876
    Abstract: A manufacturing apparatus of Group III nitride crystals and a method for manufacturing Group III nitride crystals are provided, by which high quality crystals can be manufactured. For instance, crystals are grown using the apparatus of the present invention as follows. A crystal raw material (131) and gas containing nitrogen are introduced into a reactor vessel (120), to which heat is applied by a heater (110), and crystals are grown in an atmosphere of pressure applied thereto. The gas is introduced from a gas supplying device (180) to the reactor vessel (120) through a gas inlet of the reactor vessel, and then is exhausted to the inside of a pressure-resistant vessel (102) through a gas outlet of the reactor vessel. Since the gas is introduced directly to the reactor vessel (120) without passing through the pressure-resistant vessel (102), the mixture of impurities attached to the pressure-resistant vessel (102) and the like into the site of the crystal growth can be prevented.
    Type: Application
    Filed: April 27, 2005
    Publication date: July 12, 2007
    Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Hidekazu Umeda, Yasuhito Takahashi
  • Patent number: 7092391
    Abstract: The present invention is a method for performing multi-hop peer-to-peer telecommunications on a wireless network, the topology of which changes moment by moment and which includes a plurality of radio terminals. The present invention makes possible correct routing control even on a network with severe topology changes.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: August 15, 2006
    Assignee: Skyley Networks, Inc.
    Inventor: Hidekazu Umeda
  • Publication number: 20060169197
    Abstract: A production method is provided in which Group-III-element nitride single crystals that have a lower dislocation density and a uniform thickness and are transparent, high quality, large, and bulk crystals can be produced with a high yield. The method for producing Group-III-element nitride single crystals includes: heating a reaction vessel containing at least one metal element selected from the group consisting of an alkali metal and an alkaline-earth metal and at least one Group III element selected from the group consisting of gallium (Ga), aluminum (Al), and indium (In) to prepare a flux of the metal element; and feeding nitrogen-containing gas into the reaction vessel and thereby allowing the Group III element and nitrogen to react with each other in the flux to grow Group-III-element nitride single crystals, wherein the single crystals are grown, with the flux being stirred by rocking the reaction vessel, for instance.
    Type: Application
    Filed: March 15, 2004
    Publication date: August 3, 2006
    Applicant: Osaka Industrial Promotion Organization
    Inventors: Takatamo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Hidekazu Umeda
  • Publication number: 20030161330
    Abstract: The present invention is a method for performing multi-hop peer-to-peer telecommunications on a wireless network, the topology of which changes moment by moment and which includes a plurality of radio terminals. The present invention makes possible correct routing control even on a network with severe topology changes.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: SKYLEY NETWORKS, INC.
    Inventor: Hidekazu Umeda