Patents by Inventor Hideki Eifuku

Hideki Eifuku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6209196
    Abstract: A method of mounting bumped electronic components without using a flux during the solder joining process, which is low in cost and offers high reliability of the assembly. Resin adhesive 4 containing filler particles 4a is applied to a board 1 formed with electrodes 2, and a bumped electronic component 5 is mounted onto the board 1 to press the bumps 7 of the electronic component 5 against the electrodes 2 of the board 1. As a result, the oxide films 7a over the surfaces of the solder bumps 7 are broken by the filler particles 4a present in a gap between the lower ends of the solder bumps 7 and the surfaces of the electrodes 2, thus exposing the solder. This process eliminates the need for using the flux when the solder bumps 7 are melted and soldered to the electrodes 2, and therefore the cleaning process after soldering is not required, assuring high reliability of the assembly.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: April 3, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuru Ozono, Hideki Eifuku, Tadahiko Sakai
  • Patent number: 6179198
    Abstract: A method of soldering a bumped work without using flux is provided by the steps of vacuum-sucking the bumped work on a head, pressing a bump against a pad of another work, causing a projection of the bump to partially break an oxide film on the solder portion, to pierce it, and to be placed thereon, and cooling and solidifying the molten solder portion. The surface of the solder portion is coated by the oxide film as a hard shell, so that, even if the bump is firmly pressed against the solder portion, the solder of the solder portion does not flow sidewise, and a solder bridge is not produced.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: January 30, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Eifuku, Mitsuru Ozono, Tadahiko Sakai, Shoji Sakemi
  • Patent number: 6000127
    Abstract: An electronic parts mounting method comprises a first step of forming precoatings on electrodes of a circuit board, a second step of depressing the bumps of an electronic part having bumps eat into the electrodes by pressing the electronic part having bumps to the circuit board with a mounting unit, and interposing a bonding agent between the electronic part having bumps and the circuit board, and a third step of carrying the circuit board to a thermal compression bonding unit and pressing while heating the electronic part having bumps to the circuit board with a thermal compression bonding head. This method is capable of preventing the electronic part having bumps from being deviated during carriage and allows works to be carried out in parallel with one another at a plurality of working stages, thereby enhancing a working efficiency.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: December 14, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Eifuku, Tadahiko Sakai
  • Patent number: 5962925
    Abstract: The mounting structure of an electronic component having bumps includes a multi-layer substrate provided with an outermost layer substrate having electrode on the top thereof and a lower layer substrate comprising at least one layer substrate joining the bottom of the outermost layer substrate, an electronic component having bumps bonded with the electrodes formed on the top of the outermost layer substrate for connecting the electronic component and the substrate, and under-fill resin formed between the electronic component and the outermost layer substrate, in which the coefficient of linear thermal expansion of the under-fill resin is larger than that of the electronic component, but smaller than that of the outermost layer substrate.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: October 5, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Eifuku, Tadahiko Sakai
  • Patent number: 5749510
    Abstract: A chip mounting section "H", defined on a flush surface of a substrate 1, is dissected into a plurality of subsections "E"--"E". Bond 2 is applied within the chip mounting section "H" on the flush surface of substrate 1 in a discrete manner so that a plurality of bonding bumps 2 are arranged within each region of subsection "E". A minimum clearance "L" between two bonding bumps 2, 2 in the same subsection "E" is smaller than a minimum clearance "D" between two bonding bumps 2, 2 belonging to adjacent to subsections "E" and "E". A chip 3 is mounted on plural bonding bumps 2 by applying a force thereon, thereby mashing plural bonding bumps 2 by a bottom surface of chip 3 without causing any void therein.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: May 12, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideki Eifuku