Patents by Inventor Hideki Iwaki
Hideki Iwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923672Abstract: A protection system includes: a first positive terminal; a second positive terminal; a first relay configured to be opened and closed by contact and separation of a first contact portion and a second contact portion; and a fuse.Type: GrantFiled: March 24, 2020Date of Patent: March 5, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hideki Iwaki, Hideki Watanabe
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Publication number: 20220158433Abstract: A protection system includes: a first positive terminal; a second positive terminal; a first relay configured to be opened and closed by contact and separation of a first contact portion and a second contact portion; and a fuse.Type: ApplicationFiled: March 24, 2020Publication date: May 19, 2022Inventors: HIDEKI IWAKI, HIDEKI WATANABE
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Patent number: 10575396Abstract: A circuit board includes: a substrate; a first power feed line disposed so as to be close to a plurality of radiating elements provided on a surface of the substrate and to extend in a first direction; a first connection conductor extending in a second direction orthogonal to the first direction, one end of the first connection conductor being connected to the first power feed line substantially at its central portion in the first direction; and a second power feed line that has a first line part extending in a third direction orthogonal to the second direction, the first line part joining to another end of the first connection conductor, and also has a second line part branching from the first line part, the second line part joining to the other end from a third direction side.Type: GrantFiled: March 14, 2018Date of Patent: February 25, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Ryosuke Shiozaki, Yuto Suzuki, Hideki Iwaki
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Patent number: 10141658Abstract: An antenna module includes a multilayer board, a phased array antenna that includes antenna elements arranged on an outer face of a second conductor layer included in the multilayer board and adjusts one or more beam directions of the antenna elements, a radio frequency (RF) chip that is arranged on an outer face of first conductor layers included in the multilayer board and outputs the radio frequency signal, a matching circuit that is arranged on the outer face of the first conductor layers and adjusts matching between impedance of the antenna elements and impedance of the RF chip, a through hole that couples the first conductor layers and the second conductor layer, and one or more vias that are on an outer side in a diameter direction of the through hole and couples the first conductor layers.Type: GrantFiled: May 23, 2017Date of Patent: November 27, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Chie Yamamoto, Hideki Iwaki, Ryosuke Shiozaki
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Patent number: 10122074Abstract: An antenna device comprises a dielectric substrate that has first and second surfaces; first and second antenna elements that are arranged on the first surface of the dielectric substrate; a ground conductor that is arranged on the second surface of the dielectric substrate; and an electromagnetic band gap structure that is arranged between the first and second antenna elements on the dielectric substrate. The electromagnetic band gap structure comprises: a plurality of patch conductors that are arranged on the first surface of the dielectric substrate and are electromagnetically coupled with the ground conductor; and at least one opening that is arranged in the ground conductor to expose the dielectric substrate, and causes the electromagnetic coupling between the plurality of patch conductors and the ground conductor to change.Type: GrantFiled: October 14, 2015Date of Patent: November 6, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroyoshi Tagi, Hideki Iwaki
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Publication number: 20180279466Abstract: A circuit board includes: a substrate; a first power feed line disposed so as to be close to a plurality of radiating elements provided on a surface of the substrate and to extend in a first direction; a first connection conductor extending in a second direction orthogonal to the first direction, one end of the first connection conductor being connected to the first power feed line substantially at its central portion in the first direction; and a second power feed line that has a first line part extending in a third direction orthogonal to the second direction, the first line part joining to another end of the first connection conductor, and also has a second line part branching from the first line part, the second line part joining to the other end from a third direction side.Type: ApplicationFiled: March 14, 2018Publication date: September 27, 2018Inventors: RYOSUKE SHIOZAKI, YUTO SUZUKI, HIDEKI IWAKI
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Patent number: 10014572Abstract: An antenna device of the present disclosure includes: a dielectric layer; first and second conductor layers provided on both surfaces, respectively, of the dielectric layer; first and second antenna elements provided in the first conductor layer; a grounded conductor provided in the second conductor layer; and an EBG structure provided between the first and second antenna elements, wherein the EBG structure includes a first EBG portion provided in the first conductor layer, the first EBG portion including a plurality of first patch conductors electromagnetically coupled to the grounded conductor, and a second EBG portion provided in the second conductor layer, the second EBG portion including a plurality of second patch conductors electromagnetically coupled to the grounded conductor.Type: GrantFiled: April 27, 2016Date of Patent: July 3, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroyoshi Tagi, Hideki Iwaki
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Patent number: 9960485Abstract: An antenna device comprises a first dielectric substrate; first and second antenna elements arranged on a first surface of the first dielectric substrate; a ground conductor arranged on a second surface of the first dielectric substrate; and an EBG structure arranged between the first and second antenna elements. The EBG structure comprises first patch conductors that are each arranged in contact with the first surface of the first dielectric substrate and are each electromagnetically coupled with the ground conductor; second patch conductors that are each arranged in a prescribed distance from the first surface of the first dielectric substrate in a direction opposite to the second surface, and are each electromagnetically coupled with corresponding one of the first patch conductors; and first connection conductors that electrically connect the first patch conductors with the second patch conductors.Type: GrantFiled: October 16, 2015Date of Patent: May 1, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroyoshi Tagi, Hideki Iwaki
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Publication number: 20170346195Abstract: An antenna module includes a multilayer board, a phased array antenna that includes antenna elements arranged on an outer face of a second conductor layer included in the multilayer board and adjusts one or more beam directions of the antenna elements, a radio frequency (RF) chip that is arranged on an outer face of first conductor layers included in the multilayer board and outputs the radio frequency signal, a matching circuit that is arranged on the outer face of the first conductor layers and adjusts matching between impedance of the antenna elements and impedance of the RF chip, a through hole that couples the first conductor layers and the second conductor layer, and one or more vias that are on an outer side in a diameter direction of the through hole and couples the first conductor layers.Type: ApplicationFiled: May 23, 2017Publication date: November 30, 2017Inventors: CHIE YAMAMOTO, HIDEKI IWAKI, RYOSUKE SHIOZAKI
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Publication number: 20160344093Abstract: An antenna device of the present disclosure includes: a dielectric layer; first and second conductor layers provided on both surfaces, respectively, of the dielectric layer; first and second antenna elements provided in the first conductor layer; a grounded conductor provided in the second conductor layer; and an EBG structure provided between the first and second antenna elements, wherein the EBG structure includes a first EBG portion provided in the first conductor layer, the first EBG portion including a plurality of first patch conductors electromagnetically coupled to the grounded conductor, and a second EBG portion provided in the second conductor layer, the second EBG portion including a plurality of second patch conductors electromagnetically coupled to the grounded conductor.Type: ApplicationFiled: April 27, 2016Publication date: November 24, 2016Inventors: HIROYOSHI TAGI, HIDEKI IWAKI
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Publication number: 20160141748Abstract: An antenna device comprises a dielectric substrate that has first and second surfaces; first and second antenna elements that are arranged on the first surface of the dielectric substrate; a ground conductor that is arranged on the second surface of the dielectric substrate; and an electromagnetic band gap structure that is arranged between the first and second antenna elements on the dielectric substrate. The electromagnetic band gap structure comprises: a plurality of patch conductors that are arranged on the first surface of the dielectric substrate and are electromagnetically coupled with the ground conductor; and at least one opening that is arranged in the ground conductor to expose the dielectric substrate, and causes the electromagnetic coupling between the plurality of patch conductors and the ground conductor to change.Type: ApplicationFiled: October 14, 2015Publication date: May 19, 2016Inventors: HIROYOSHI TAGI, HIDEKI IWAKI
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Publication number: 20160141749Abstract: An antenna device comprises a first dielectric substrate; first and second antenna elements arranged on a first surface of the first dielectric substrate; a ground conductor arranged on a second surface of the first dielectric substrate; and an EBG structure arranged between the first and second antenna elements. The EBG structure comprises first patch conductors that are each arranged in contact with the first surface of the first dielectric substrate and are each electromagnetically coupled with the ground conductor; second patch conductors that are each arranged in a prescribed distance from the first surface of the first dielectric substrate in a direction opposite to the second surface, and are each electromagnetically coupled with corresponding one of the first patch conductors; and first connection conductors that electrically connect the first patch conductors with the second patch conductors.Type: ApplicationFiled: October 16, 2015Publication date: May 19, 2016Inventors: HIROYOSHI TAGI, HIDEKI IWAKI
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Patent number: 8344264Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.Type: GrantFiled: June 23, 2009Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Yutaka Kumano, Hideki Iwaki, Tetsuyoshi Ogura, Shingo Komatsu, Koichi Hirano
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Patent number: 8290451Abstract: In a noise reduction circuit, a transistor circuit amplifies an input signal and outputs an output signal with supply of power from the DC voltage source via a power supply line circuit. The canceling signal adding circuit acquires and attenuates a part of the output signal, to generate a canceling signal having a phase substantially opposite to a phase of a leakage signal leaking to the power supply line circuit, and having an amplitude substantially the same as an amplitude of the leakage signal.Type: GrantFiled: March 28, 2007Date of Patent: October 16, 2012Assignee: Panasonic CorporationInventors: Naoki Komatsu, Hideki Iwaki, Toru Yamada
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Patent number: 7814445Abstract: An interference analysis device that analyzes interference includes an input unit that inputs design data, a selection unit that selects an analysis region, a division unit that divides a wire into segments, a calculation unit that calculates a circuit matrix regarding a coupled line, and an analysis unit that obtains a degree of electromagnetic interference, wherein the calculation unit calculates a circuit matrix of the coupled line, using a parameter set obtained by adding an asymmetry parameter to RLGC parameters of a transmission line in the coupled line. Thus, a method for analyzing an interference of circuit wiring can be provided, which is capable of shortening a processing time substantially while maintaining high precision.Type: GrantFiled: April 14, 2006Date of Patent: October 12, 2010Assignee: Panasonic CorporationInventors: Hideki Iwaki, Naoki Komatsu, Tetsuyoshi Ogura, Toru Yamada
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Patent number: 7788076Abstract: An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.Type: GrantFiled: March 8, 2005Date of Patent: August 31, 2010Assignee: Panasonic CorporationInventors: Hideki Iwaki, Tetsuyoshi Ogura, Naoki Komatsu, Takeshi Nakayama, Tomohiro Kinoshita
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Publication number: 20090321124Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.Type: ApplicationFiled: June 23, 2009Publication date: December 31, 2009Inventors: Yutaka KUMANO, Hideki IWAKI, Tetsuyoshi OGURA, Shingo KOMATSU, Koichi HIRANO
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Publication number: 20090174476Abstract: In a noise reduction circuit, a transistor circuit amplifies an input signal and outputs an output signal with supply of power from the DC voltage source via a power supply line circuit. The canceling signal adding circuit acquires and attenuates a part of the output signal, to generate a canceling signal having a phase substantially opposite to a phase of a leakage signal leaking to the power supply line circuit, and having an amplitude substantially the same as an amplitude of the leakage signal.Type: ApplicationFiled: March 28, 2007Publication date: July 9, 2009Inventors: Naoki Komatsu, Hideki Iwaki, Toru Yamada
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Publication number: 20090019403Abstract: An interference analysis device that analyzes interference includes an input unit 2 that inputs design data, a selection unit 3 that selects an analysis region, a division unit 5 that divides a wire into segments, a calculation unit 6 that calculates a circuit matrix regarding a coupled line, and an analysis unit 7 that obtains a degree of electromagnetic interference, wherein the calculation unit 6 calculates a circuit matrix of the coupled line, using a parameter set obtained by adding an asymmetry parameter to RLGC parameters of a transmission line in the coupled line. Thus, a method for analyzing an interference of circuit wiring can be provided, which is capable of shortening a processing time substantially while maintaining high precision.Type: ApplicationFiled: April 14, 2006Publication date: January 15, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hideki Iwaki, Naoki Komatsu, Tetsuyoshi Ogura, Toru Yamada
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Patent number: 7385286Abstract: At least four terminal electrodes are provided on a surface of multi-layer substrate main body. An electric functional layer is selectively provided at an internal area of said multi-layer substrate placed at a downward position of all terminal electrodes in a substrate thickness direction. A semiconductor device is flip-chip-bonded to the terminal electrodes. Thus, the semiconductor device is electrically connected to the electric functional layer at a short distance. As a result, a reduction in parasitic inductance and an improvement in high frequency characteristic can be accomplished. Generation of height variations between the terminal electrodes can be prevented, and the semiconductor device is stably flip-chip-bonded to the multi-layer substrate.Type: GrantFiled: June 5, 2002Date of Patent: June 10, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Iwaki, Tetsuyoshi Ogura, Yutaka Taguchi