Patents by Inventor Hideki Kitada

Hideki Kitada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100123480
    Abstract: A semiconductor device that includes multiple logic circuit cells having respective logic circuits formed therein and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.
    Type: Application
    Filed: January 22, 2010
    Publication date: May 20, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hideki KITADA, Takahiro KIMURA
  • Patent number: 7713869
    Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: May 11, 2010
    Assignee: Fujitsu Limited
    Inventors: Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao
  • Patent number: 7670925
    Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: March 2, 2010
    Assignee: Fujitsu Limited
    Inventors: Hideki Kitada, Takahiro Kimura
  • Publication number: 20100007023
    Abstract: (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Yumiko Koura, Hideki Kitada, Kiyoshi Ozawa
  • Patent number: 7611984
    Abstract: (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: November 3, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yumiko Koura, Hideki Kitada, Kiyoshi Ozawa
  • Patent number: 7507666
    Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: March 24, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
  • Publication number: 20080286960
    Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Application
    Filed: July 11, 2008
    Publication date: November 20, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Publication number: 20080211098
    Abstract: A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed.
    Type: Application
    Filed: January 24, 2008
    Publication date: September 4, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi SUZUKI, Hideki KITADA
  • Patent number: 7416985
    Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Tamotsu Yamamoto, Hirofumi Watani, Hideki Kitada, Hiroshi Horiuchi, Motoshu Miyajima
  • Patent number: 7413977
    Abstract: A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. Then the semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: August 19, 2008
    Assignee: Fujitsu Limited
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Publication number: 20080150586
    Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 26, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hideki Kitada, Takahiro Kimura
  • Patent number: 7329952
    Abstract: The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The unit patterns 26c of the dummy pattern are formed in the density of 10-25%. Even in the case that the electrolytic plating solution for bottom up growth mechanism is used, the step on the surface of a copper film due to over-plating can be decreased, and the total plating thickness necessary to fill the interconnection trenches can be decreased.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: February 12, 2008
    Assignee: Fujitsu Limited
    Inventors: Hideki Kitada, Noriyoshi Shimizu
  • Publication number: 20070273156
    Abstract: An object is to provide a wave power generator which can convert wave energy to electric energy with high efficiency and supply electric power of a large capacity at low cost and has a simple structure and is low in construction cost. The wave power generator includes a heavy body 3 elastically supported by air springs 4 as elastic members in an enclosing wall 2 on a floating body 1 and an electromagnetic damper as a generating means 7 provided between the heavy body 3 and the floating body 1. The spring constant of the air springs 4 is adjustable by providing auxiliary tanks in the piston 6 and the floating body 1 so that the undamped natural frequency of the air spring is equal to or close to the frequency of waves within a predetermined frequency ratio ?/?0. Thus, the frequency of the spring system resonates with the frequency of waves, so that the relative movement of the power generating means 7 increases to a maximum and power generation is carried out with maximum efficiency.
    Type: Application
    Filed: October 14, 2004
    Publication date: November 29, 2007
    Inventors: Koji Miyajima, Hideki Kitada
  • Patent number: 7279790
    Abstract: A multilayer interconnection structure that offers a fast semiconductor operation is realized by employing copper wiring, electro migration of which is prevented from occurring by providing a via plug that includes a layer of a high melting-point metal, such as tungsten.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: October 9, 2007
    Assignee: Fujitsu Limited
    Inventors: Hideki Kitada, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Takayuki Ohba
  • Publication number: 20070161242
    Abstract: A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made of insulating material is formed over the first interlayer insulating film. A wiring groove is formed in the second interlayer insulating film, passing over the conductive plug and exposing the upper surface of the conductive plug. A wiring made of copper or alloy mainly consisting of copper is filled in the wiring groove. The total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug is lower than the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.
    Type: Application
    Filed: March 7, 2007
    Publication date: July 12, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yumiko Koura, Hideki Kitada
  • Patent number: 7205667
    Abstract: A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made of insulating material is formed over the first interlayer insulating film. A wiring groove is formed in the second interlayer insulating film, passing over the conductive plug and exposing the upper surface of the conductive plug. A wiring made of copper or alloy mainly consisting of copper is filled in the wiring groove. The total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug is lower than the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: April 17, 2007
    Assignee: Fujitsu Limited
    Inventors: Yumiko Koura, Hideki Kitada
  • Publication number: 20070049024
    Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.
    Type: Application
    Filed: December 6, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
  • Publication number: 20070045851
    Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.
    Type: Application
    Filed: November 30, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao
  • Publication number: 20070048931
    Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.
    Type: Application
    Filed: December 28, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
  • Publication number: 20070020931
    Abstract: (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film.
    Type: Application
    Filed: October 14, 2005
    Publication date: January 25, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yumiko Koura, Hideki Kitada, Kiyoshi Ozawa